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| author | Wolfgang Denk <wd@pollux.denx.de> | 2006-03-12 02:55:22 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.denx.de> | 2006-03-12 02:55:22 +0100 |
| commit | 8e7b703a62783f0e88d3a7e4b1dd1c033bc95ec8 (patch) | |
| tree | 24c189eb88f7864177be3645e48b44e6e50d6304 /cpu/bf533/cache.S | |
| parent | 1264b4050c6f635cc237b5821f924817457ce50c (diff) | |
| download | u-boot-imx-8e7b703a62783f0e88d3a7e4b1dd1c033bc95ec8.zip u-boot-imx-8e7b703a62783f0e88d3a7e4b1dd1c033bc95ec8.tar.gz u-boot-imx-8e7b703a62783f0e88d3a7e4b1dd1c033bc95ec8.tar.bz2 | |
Coding Style cleanup
Diffstat (limited to 'cpu/bf533/cache.S')
| -rw-r--r-- | cpu/bf533/cache.S | 144 |
1 files changed, 72 insertions, 72 deletions
diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S index 1822d1f..8fac402 100644 --- a/cpu/bf533/cache.S +++ b/cpu/bf533/cache.S @@ -22,88 +22,88 @@ ENTRY(blackfin_icache_flush_range) ENTRY(blackfin_dcache_flush_range) R2 = -32; - R2 = R0 & R2; - P0 = R2; - P1 = R1; - CSYNC; + R2 = R0 & R2; + P0 = R2; + P1 = R1; + CSYNC; 1: - FLUSH[P0++]; - CC = P0 < P1(iu); - IF CC JUMP 1b(bp); - FLUSH[P0]; - SSYNC; - RTS; + FLUSH[P0++]; + CC = P0 < P1(iu); + IF CC JUMP 1b(bp); + FLUSH[P0]; + SSYNC; + RTS; ENTRY(_icache_invalidate) ENTRY(invalidate_entire_icache) - [--SP] = ( R7:5); - - P0.L = (IMEM_CONTROL & 0xFFFF); - P0.H = (IMEM_CONTROL >> 16); - R7 = [P0]; - - /* Clear the IMC bit , All valid bits in the instruction - * cache are set to the invalid state - */ - BITCLR(R7,IMC_P); - CLI R6; - SSYNC; /* SSYNC required before invalidating cache. */ - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - /* Configures the instruction cache agian */ - R6 = (IMC | ENICPLB); - R7 = R7 | R6; - - CLI R6; - SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - ( R7:5) = [SP++]; - RTS; + [--SP] = ( R7:5); + + P0.L = (IMEM_CONTROL & 0xFFFF); + P0.H = (IMEM_CONTROL >> 16); + R7 = [P0]; + + /* Clear the IMC bit , All valid bits in the instruction + * cache are set to the invalid state + */ + BITCLR(R7,IMC_P); + CLI R6; + SSYNC; /* SSYNC required before invalidating cache. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + /* Configures the instruction cache agian */ + R6 = (IMC | ENICPLB); + R7 = R7 | R6; + + CLI R6; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + ( R7:5) = [SP++]; + RTS; /* Invalidate the Entire Data cache by * clearing DMC[1:0] bits */ ENTRY(invalidate_entire_dcache) ENTRY(_dcache_invalidate) - [--SP] = ( R7:6); - - P0.L = (DMEM_CONTROL & 0xFFFF); - P0.H = (DMEM_CONTROL >> 16); - R7 = [P0]; - - /* Clear the DMC[1:0] bits, All valid bits in the data - * cache are set to the invalid state - */ - BITCLR(R7,DMC0_P); - BITCLR(R7,DMC1_P); - CLI R6; - SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - /* Configures the data cache again */ - - R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - R7 = R7 | R6; - - CLI R6; - SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - ( R7:6) = [SP++]; - RTS; + [--SP] = ( R7:6); + + P0.L = (DMEM_CONTROL & 0xFFFF); + P0.H = (DMEM_CONTROL >> 16); + R7 = [P0]; + + /* Clear the DMC[1:0] bits, All valid bits in the data + * cache are set to the invalid state + */ + BITCLR(R7,DMC0_P); + BITCLR(R7,DMC1_P); + CLI R6; + SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + /* Configures the data cache again */ + + R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0); + R7 = R7 | R6; + + CLI R6; + SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + ( R7:6) = [SP++]; + RTS; ENTRY(blackfin_dcache_invalidate_range) R2 = -32; |