diff options
| author | Nishanth Menon <nm@ti.com> | 2009-11-09 09:29:34 -0500 |
|---|---|---|
| committer | Tom Rix <Tom.Rix@windriver.com> | 2009-11-27 16:26:17 -0600 |
| commit | d414aae552bc229dafcad92028effb4a8306c7a5 (patch) | |
| tree | 61893df2fd2a1685b47fb28fd7411b8afd288049 /cpu/arm_cortexa8 | |
| parent | 30563a04bff73fd4fbd840b846f4b6459759a839 (diff) | |
| download | u-boot-imx-d414aae552bc229dafcad92028effb4a8306c7a5.zip u-boot-imx-d414aae552bc229dafcad92028effb4a8306c7a5.tar.gz u-boot-imx-d414aae552bc229dafcad92028effb4a8306c7a5.tar.bz2 | |
OMAP3: Fix SDRC init
Defaults are for Infineon DDR timings.
Since none of the supported boards currently do
XIP boot, these seem to be faulty. fix the values
as per the calculations(ACTIMA,B), conf
the sdrc power with pwdnen and wakeupproc bits
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'cpu/arm_cortexa8')
| -rw-r--r-- | cpu/arm_cortexa8/omap3/mem.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index 2c2d4f7..dfb7e4c 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -164,7 +164,8 @@ void do_sdrc_init(u32 cs, u32 early) writel(SDRC_SHARING, &sdrc_base->sharing); /* Disable Power Down of CKE cuz of 1 CKE on combo part */ - writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power); + writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH, + &sdrc_base->power); writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); |