diff options
author | Kim, Heung Jun <riverful@gmail.com> | 2009-06-20 11:02:17 +0200 |
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committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-07-06 21:52:25 +0200 |
commit | 06e758e75c79ce8761866bf8165c443584a20893 (patch) | |
tree | ad667c552c3e9ed2e12117b1144beffb49c416d1 /cpu/arm_cortexa8/omap3 | |
parent | d583ef5147066d3609de21f3beebbab99a19bad4 (diff) | |
download | u-boot-imx-06e758e75c79ce8761866bf8165c443584a20893.zip u-boot-imx-06e758e75c79ce8761866bf8165c443584a20893.tar.gz u-boot-imx-06e758e75c79ce8761866bf8165c443584a20893.tar.bz2 |
move L2 cache enable/disable function to cache.c in the omap3 SoC directory
Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
CC: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'cpu/arm_cortexa8/omap3')
-rw-r--r-- | cpu/arm_cortexa8/omap3/Makefile | 1 | ||||
-rw-r--r-- | cpu/arm_cortexa8/omap3/board.c | 5 | ||||
-rw-r--r-- | cpu/arm_cortexa8/omap3/cache.c | 96 |
3 files changed, 100 insertions, 2 deletions
diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile index 50176ee..1fbd0dc 100644 --- a/cpu/arm_cortexa8/omap3/Makefile +++ b/cpu/arm_cortexa8/omap3/Makefile @@ -28,6 +28,7 @@ LIB = $(obj)lib$(SOC).a SOBJS := lowlevel_init.o COBJS += board.o +COBJS += cache.o COBJS += clock.o COBJS += gpio.o COBJS += mem.o diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 6e29599..b665ec9 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -36,6 +36,7 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> +#include <asm/cache.h> extern omap3_sysinfo sysinfo; @@ -206,9 +207,9 @@ void s_init(void) #endif #ifdef CONFIG_L2_OFF - l2cache_disable(); + l2_cache_disable(); #else - l2cache_enable(); + l2_cache_enable(); #endif /* * Writing to AuxCR in U-boot using SMI for GP DEV diff --git a/cpu/arm_cortexa8/omap3/cache.c b/cpu/arm_cortexa8/omap3/cache.c new file mode 100644 index 0000000..f49ed4a --- /dev/null +++ b/cpu/arm_cortexa8/omap3/cache.c @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * omap3 L2 cache code + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/cache.h> + +void l2_cache_enable(void) +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("orr r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } + +} + +void l2_cache_disable(void) +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("bic r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } +} + |