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| author | Sammy He <r62914@freescale.com> | 2011-03-18 20:58:17 +0800 |
|---|---|---|
| committer | Sammy He <r62914@freescale.com> | 2011-03-21 21:19:47 +0800 |
| commit | ac48999b9353d038e95f965af08184dc6342adfc (patch) | |
| tree | 0d5a248ac8e50a19047ab135e9348e8612b73b41 /cpu/arm_cortexa8/mx50 | |
| parent | 32ab6b2785b763588644e766235e2ed21a853c2a (diff) | |
| download | u-boot-imx-ac48999b9353d038e95f965af08184dc6342adfc.zip u-boot-imx-ac48999b9353d038e95f965af08184dc6342adfc.tar.gz u-boot-imx-ac48999b9353d038e95f965af08184dc6342adfc.tar.bz2 | |
ENGR00140824 Android: Enable fastboot support for mx50 rdp
Enable fastboot support for mx50 rdp.
Signed-off-by: Sammy He <r62914@freescale.com>
Diffstat (limited to 'cpu/arm_cortexa8/mx50')
| -rw-r--r-- | cpu/arm_cortexa8/mx50/crm_regs.h | 14 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/mx50/generic.c | 51 |
2 files changed, 62 insertions, 3 deletions
diff --git a/cpu/arm_cortexa8/mx50/crm_regs.h b/cpu/arm_cortexa8/mx50/crm_regs.h index 1af5f9e..4408355 100644 --- a/cpu/arm_cortexa8/mx50/crm_regs.h +++ b/cpu/arm_cortexa8/mx50/crm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -190,10 +190,14 @@ #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) -#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET (21) -#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 21) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET (21) +#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 21) #define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 20) #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 19) #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET (16) @@ -220,6 +224,10 @@ #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) #define MXC_CCM_CSCDR1_ESDHC1_CLK_PODF_OFFSET (11) #define MXC_CCM_CSCDR1_ESDHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) diff --git a/cpu/arm_cortexa8/mx50/generic.c b/cpu/arm_cortexa8/mx50/generic.c index a964218..e1f55d1 100644 --- a/cpu/arm_cortexa8/mx50/generic.c +++ b/cpu/arm_cortexa8/mx50/generic.c @@ -545,6 +545,57 @@ static u32 __get_bch_clk(void) #endif +void set_usboh3_clk(void) +{ + unsigned int reg; + + reg = readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; + reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; + writel(reg, MXC_CCM_CSCMR1); + + reg = readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK; + reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET; + reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET; + + writel(reg, MXC_CCM_CSCDR1); +} + +void set_usb_phy1_clk(void) +{ + unsigned int reg; + + reg = readl(MXC_CCM_CSCMR1); + reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + writel(reg, MXC_CCM_CSCMR1); +} + +void enable_usboh3_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(MXC_CCM_CCGR2); + if (enable) + reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET); + writel(reg, MXC_CCM_CCGR2); +} + +void enable_usb_phy1_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(MXC_CCM_CCGR4); + if (enable) + reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET); + writel(reg, MXC_CCM_CCGR4); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { |