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authorBin Meng <bmeng.cn@gmail.com>2015-09-14 00:07:41 -0700
committerSimon Glass <sjg@chromium.org>2015-09-16 19:53:53 -0600
commitc6d4705f41d4e45e8cecc6e08b0b89df1ffe57ef (patch)
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parent0993fc026b5003cfc7da9abe8a3fddbd26c7ee44 (diff)
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x86: quark: Configure MTRR to enable cache
Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs are accessed indirectly via the message port and not the traditional MSR mechanism. Only UC, WT and WB cache types are supported. We configure all the fixed range MTRRs with common values (VGA RAM as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as WB, which significantly improves the boot time performance. With this commit, it takes only 2 seconds for U-Boot to boot to shell on Intel Galileo board. Previously it took about 6 seconds. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
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