MLK-12329-1 imx7d: Update DDR script for TO1.1

On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend
 mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated.
When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards),
DDR data corruption occured, not able to decrease CKE delay, so we have to add extra
delay on all other signals to balance it.
DDR script needs to be fine-tuned according to this hardware change.

For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from
533Mhz to 400Mhz.

Compass link:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=name

Test:
Overnight tests passed on all changed boards.

Signed-off-by: Ye Li <ye.li@nxp.com>

0 files changed, 0 insertions, 0 deletions