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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-10-11 21:37:44 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-10-21 07:46:27 -0600 |
| commit | 638a05894169b07ea8f6d21b6925ca353ea6ebb7 (patch) | |
| tree | 68308063e00f4b803a07b9f55d56b2973edc2c7b /configs | |
| parent | 8b185041a9f4c30dc5edb1e04c0834e931b8633f (diff) | |
| download | u-boot-imx-638a05894169b07ea8f6d21b6925ca353ea6ebb7.zip u-boot-imx-638a05894169b07ea8f6d21b6925ca353ea6ebb7.tar.gz u-boot-imx-638a05894169b07ea8f6d21b6925ca353ea6ebb7.tar.bz2 | |
x86: Enable mrc cache for bayleybay and minnowmax
Now that we have added MRC cache for Intel FSP and BayTrail codes,
enable it for all BayTrail boards (Bayley Bay and Minnow Max).
Note it turns out that FSP for Intel Atom E6xx does not produce
the HOB for NV storage, so we don't have such functionality on
Intel Crown Bay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/bayleybay_defconfig | 1 | ||||
| -rw-r--r-- | configs/minnowmax_defconfig | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 56316ee..fc40da8 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="bayleybay" CONFIG_TARGET_BAYLEYBAY=y CONFIG_HAVE_INTEL_ME=y +CONFIG_ENABLE_MRC_CACHE=y CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_VGA_BIOS_ADDR=0xfffa0000 diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 0d5bd4e..8f99f0e 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="minnowmax" CONFIG_TARGET_MINNOWMAX=y CONFIG_HAVE_INTEL_ME=y +CONFIG_ENABLE_MRC_CACHE=y CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y |