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author | Michal Simek <michal.simek@xilinx.com> | 2016-07-15 08:41:46 +0200 |
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committer | Michal Simek <michal.simek@xilinx.com> | 2016-07-22 14:04:35 +0200 |
commit | f3d1cc2ff387ffe22ccd1bdcb2a998ec46149c6d (patch) | |
tree | 92a2fa164df6ceb0bd4a88b33dcf14db75e4c88f /configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | |
parent | 1f29738ad13ad178185490db0bb17ad71343e251 (diff) | |
download | u-boot-imx-f3d1cc2ff387ffe22ccd1bdcb2a998ec46149c6d.zip u-boot-imx-f3d1cc2ff387ffe22ccd1bdcb2a998ec46149c6d.tar.gz u-boot-imx-f3d1cc2ff387ffe22ccd1bdcb2a998ec46149c6d.tar.bz2 |
ARM64: zynqmp: Enable SPL for all zynqmp boards
Compile SPL for all boards even psu_init.c/h files are not in the tree
yet. But this change enables covering SPL issues in mainline.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig')
-rw-r--r-- | configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index 4342e05..efa7b8c 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -2,10 +2,13 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm018_dc4" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_DM=y CONFIG_DM_I2C=y CONFIG_DM_GPIO=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4" +CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y @@ -27,8 +30,10 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y |