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authorKotaro Hayashi <hayashi.kotaro@socionext.com>2017-02-14 11:39:14 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2017-02-23 08:37:56 +0900
commit04f3da393667b094adc4fef37db71c7327d5ed7d (patch)
treec0e57e4a87166c89e4d1053edacecf85ffb00e0f /configs/pdm360ng_defconfig
parentdd38374d2f1d89fb34d4c544f558537db1966a33 (diff)
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ARM: uniphier: add DRAM PHY clock duty adjustment for LD20 SoC
If the DRAM clock duty does not meet the allowable tolerance, it is marked in an efuse register. If the register is fused, the boot code should compensate for the DRAM clock duty error. Signed-off-by: Kotaro Hayashi <hayashi.kotaro@socionext.com> [masahiro: simplify code, add git-log] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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