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| author | Bibek Basu <bbasu@nvidia.com> | 2016-08-11 16:28:28 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2016-08-15 10:26:14 -0700 |
| commit | b064c9124acddbcdc70843f62fda13a2d7d7a392 (patch) | |
| tree | b54a420cf982cbee21b87ae5c94b669a89726ecc /configs/openrisc-generic_defconfig | |
| parent | 027638d3cf6bf55996b50e41faccd51789a04eb0 (diff) | |
| download | u-boot-imx-b064c9124acddbcdc70843f62fda13a2d7d7a392.zip u-boot-imx-b064c9124acddbcdc70843f62fda13a2d7d7a392.tar.gz u-boot-imx-b064c9124acddbcdc70843f62fda13a2d7d7a392.tar.bz2 | |
ARM: tegra: set vdd_core for Jetson TK1
Program vdd_core for Jetson TK1 to 1V, which is the max safe voltage for
ultra low temperature operations. vdd_cpu and vdd_gpu are already at 1V.
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
(swarren: fixed comments to better match the code)
(swarren: moved board ifdef around data in header, made code generic)
(swarren: fixed typos in commit description)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'configs/openrisc-generic_defconfig')
0 files changed, 0 insertions, 0 deletions