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| author | Ye Li <ye.li@nxp.com> | 2017-03-15 16:53:31 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 17:24:31 +0800 |
| commit | 5a69ddb7e9886e082da42ddf673415702975ee60 (patch) | |
| tree | 647445422a61332d8a2b0ff4b934081666a3f425 /configs/mx6sxsabreauto_nand_defconfig | |
| parent | cafc860907a408156a43fa20169dfc187648618e (diff) | |
| download | u-boot-imx-5a69ddb7e9886e082da42ddf673415702975ee60.zip u-boot-imx-5a69ddb7e9886e082da42ddf673415702975ee60.tar.gz u-boot-imx-5a69ddb7e9886e082da42ddf673415702975ee60.tar.bz2 | |
MLK-13450-16 fsl_qspi: Update changes for mx7ulp
The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes)
than other i.MX. Change some parameters for it.
Also found when the DDR_EN bit is set, sometime the page programming will fail
during large data programming. The 64 bytes data is not programmed into flash.
But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue.
We have disable the DDR_EN for mx7ulp.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'configs/mx6sxsabreauto_nand_defconfig')
0 files changed, 0 insertions, 0 deletions