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| author | Ye Li <ye.li@nxp.com> | 2016-03-09 16:13:48 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-03-25 13:55:54 +0100 |
| commit | b777789ebd193587a8e4700dce656523df821370 (patch) | |
| tree | 9afc5474db13a66b5d16e9a612db7a6f666038e9 /configs/mx53ard_defconfig | |
| parent | 312a6c016a2d81aa3fbc605f5c0c315b6a4e3464 (diff) | |
| download | u-boot-imx-b777789ebd193587a8e4700dce656523df821370.zip u-boot-imx-b777789ebd193587a8e4700dce656523df821370.tar.gz u-boot-imx-b777789ebd193587a8e4700dce656523df821370.tar.bz2 | |
imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'configs/mx53ard_defconfig')
0 files changed, 0 insertions, 0 deletions