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| author | Kever Yang <kever.yang@rock-chips.com> | 2016-09-23 15:57:17 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2016-10-01 18:35:01 -0600 |
| commit | 8389dcbf98b756d01b0b31679d3b83119382ac51 (patch) | |
| tree | ce96b4776c29ca1ed30b5420fec5a738682edbf1 /configs/Yones_Toptech_BS1078_V2_defconfig | |
| parent | e73e5fcd8498b5db7bb604ef2223d636a54505ff (diff) | |
| download | u-boot-imx-8389dcbf98b756d01b0b31679d3b83119382ac51.zip u-boot-imx-8389dcbf98b756d01b0b31679d3b83119382ac51.tar.gz u-boot-imx-8389dcbf98b756d01b0b31679d3b83119382ac51.tar.bz2 | |
rockchip: rk3399: update PPLL and pmu_pclk frequency
Update PPLL to 676MHz and PMU_PCLK to 48MHz, because:
1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz
can not,
2. We think 48MHz is fast enough for pmu pclk and it is lower power cost
than 99MHz,
3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using
internally for kernel,it suppose not to change the bus clock like pmu_pclk
in kernel, so we want to change it in uboot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'configs/Yones_Toptech_BS1078_V2_defconfig')
0 files changed, 0 insertions, 0 deletions