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author | Siarhei Siamashka <siarhei.siamashka@gmail.com> | 2014-08-03 05:32:46 +0300 |
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committer | Hans de Goede <hdegoede@redhat.com> | 2014-08-12 08:42:33 +0200 |
commit | 5c18384dea60a9acbbc6f2f95a5e291089db7e94 (patch) | |
tree | 4594f7dd4d9cfee94ad857627e29f977cffbf347 /configs/P5020DS_SRIO_PCIE_BOOT_defconfig | |
parent | 94cd3019881523b7776138f93f9e6b9849adc4d4 (diff) | |
download | u-boot-imx-5c18384dea60a9acbbc6f2f95a5e291089db7e94.zip u-boot-imx-5c18384dea60a9acbbc6f2f95a5e291089db7e94.tar.gz u-boot-imx-5c18384dea60a9acbbc6f2f95a5e291089db7e94.tar.bz2 |
sunxi: dram: Re-introduce the impedance calibration ond ODT
The DRAM controller allows to configure impedance either by using the
calibration against an external high precision 240 ohm resistor, or
by skipping the calibration and loading pre-defined data. The DRAM
controller register guide is available here:
http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_ZQCR0
The new code supports both of the impedance configuration modes:
- If the higher bits of the 'zq' parameter in the 'dram_para' struct
are zero, then the lowest 8 bits are used as the ZPROG value, where
two divisors encoded in lower and higher 4 bits. One divisor is
used for calibrating the termination impedance, and another is used
for the output impedance.
- If bits 27:8 in the 'zq' parameters are non-zero, then they are
used as the pre-defined ZDATA value instead of performing the ZQ
calibration.
Two lowest bits in the 'odt_en' parameter enable ODT for the DQ and DQS
lines individually. Enabling ODT for both DQ and DQS means that the
'odt_en' parameter needs to be set to 3.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'configs/P5020DS_SRIO_PCIE_BOOT_defconfig')
0 files changed, 0 insertions, 0 deletions