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authorSimon Glass <sjg@chromium.org>2015-08-10 07:14:36 -0600
committerTom Warren <twarren@nvidia.com>2015-08-13 13:06:04 -0700
commit5a30cee5d05f0ef0470b85f94907022704598253 (patch)
treec0cf4cf1f57b09c09be1dfd12a543b991a82ce0d /configs/P1010RDB-PB_36BIT_NAND_defconfig
parent35f590f4c3300f1aa6bcd2c69ff2f96839cdd85c (diff)
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tegra: Correct logic for reading pll_misc in clock_start_pll()
The logic for simple PLLs on T124 was broken by this commit: 722e000c Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. Correct it by reading from the same pll_misc register that it writes to and adding an entry for the DP PLL in the pllinfo table. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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