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authorPeng Fan <peng.fan@nxp.com>2016-01-06 11:06:31 +0800
committerStefano Babic <sbabic@denx.de>2016-01-24 12:13:21 +0100
commit9ba18ff8efcc471635fb2768509fed025fa7db3c (patch)
treee30126c87d2fff657f6cbcf14b37df543dde9194 /common/xyzModem.c
parent234dc6330126e2c16f45821be9f52862aecda030 (diff)
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imx: mx6ul/sx: fix mmdc_ch0 clk calculation
Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications Processor Reference Manual and "Figure 18-5. BUS clock generation" of i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk sources from pll4_main_clk(pll_audio), the calculation is wrong. Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support for decode_pll. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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