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| author | Adam Graham <agraham@amcc.com> | 2008-10-06 10:16:13 -0700 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-10-08 11:36:23 +0200 |
| commit | f8a00dea841d5d75de1f8e8107e90ee1beeddf5f (patch) | |
| tree | 819dece576ce94a497c9c95dd5a1c917efd84980 /board | |
| parent | 50a874b3b0272f32e3627732fab90b27fbd35066 (diff) | |
| download | u-boot-imx-f8a00dea841d5d75de1f8e8107e90ee1beeddf5f.zip u-boot-imx-f8a00dea841d5d75de1f8e8107e90ee1beeddf5f.tar.gz u-boot-imx-f8a00dea841d5d75de1f8e8107e90ee1beeddf5f.tar.bz2 | |
ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change
After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board')
0 files changed, 0 insertions, 0 deletions