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authorAlexander Graf <agraf@suse.de>2016-03-04 01:09:51 +0100
committerTom Rini <trini@konsulko.com>2016-03-15 15:13:04 -0400
commite593bf5eb36669a5f8a55271eb8c14cb4cf93961 (patch)
tree39637cde579db74011816a0e2a542d92e2c6d38f /board
parentb30291a3b212f48927daa81dc64b88a3927c5609 (diff)
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vexpress64: Add MMU tables
There's no good excuse for running with caches disabled on AArch64, so let's just move the vexpress64 target to enable the MMU and run with caches on. Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'board')
-rw-r--r--board/armltd/vexpress64/vexpress64.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 6efc8c1..973b579 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -14,6 +14,7 @@
#include <dm/platdata.h>
#include <dm/platform_data/serial_pl01x.h>
#include "pcie.h"
+#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -28,6 +29,26 @@ U_BOOT_DEVICE(vexpress_serials) = {
.platdata = &serial_platdata,
};
+static struct mm_region vexpress64_mem_map[] = {
+ {
+ .base = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .base = 0x80000000UL,
+ .size = 0xff80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = vexpress64_mem_map;
+
/* This function gets replaced by platforms supporting PCIe.
* The replacement function, eg. on Juno, initialises the PCIe bus.
*/