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authorTom Rini <trini@konsulko.com>2015-04-28 12:15:13 -0400
committerTom Rini <trini@konsulko.com>2015-04-28 12:15:13 -0400
commite536ab8849b2b4f6d68bbc8e1d1f9bc033db06bd (patch)
treee5e3a3d5a0bee8a1d9a74deb3990455c40ded6b1 /board
parentcc555bd4f40a652471df4a3621d45ee57df0ca11 (diff)
parent205d58699b157df75f1aa0b363ea9c21add21a0c (diff)
downloadu-boot-imx-e536ab8849b2b4f6d68bbc8e1d1f9bc033db06bd.zip
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Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'board')
-rw-r--r--board/freescale/common/Makefile3
-rw-r--r--board/freescale/mx6sabresd/mx6sabresd.c13
-rw-r--r--board/gateworks/gw_ventana/eeprom.c10
-rw-r--r--board/gateworks/gw_ventana/gsc.c130
-rw-r--r--board/gateworks/gw_ventana/gsc.h10
-rw-r--r--board/gateworks/gw_ventana/gw_ventana.c367
-rw-r--r--board/gateworks/gw_ventana/gw_ventana_spl.c129
-rw-r--r--board/gateworks/gw_ventana/ventana_eeprom.h1
-rw-r--r--board/solidrun/mx6cuboxi/Kconfig15
-rw-r--r--board/solidrun/mx6cuboxi/MAINTAINERS6
-rw-r--r--board/solidrun/mx6cuboxi/Makefile9
-rw-r--r--board/solidrun/mx6cuboxi/README21
-rw-r--r--board/solidrun/mx6cuboxi/mx6cuboxi.c510
13 files changed, 1100 insertions, 124 deletions
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 7181cac..87d0578 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -74,8 +74,7 @@ obj-$(CONFIG_P5040DS) += p_corenet/
obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o
ifdef CONFIG_SECURE_BOOT
-obj-y += fsl_validate.o
-obj-$(CONFIG_CMD_ESBC_VALIDATE) += cmd_esbc_validate.o
+obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
endif
endif
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index bb2dd96..23f8f6b 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -753,10 +753,11 @@ const struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p1_mpwrdlctl = 0x48254A36,
};
+/* MT41K128M16JT-125 */
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 1600,
- .density = 4,
- .width = 64,
+ .density = 2,
+ .width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
@@ -798,18 +799,14 @@ static void spl_dram_init(void)
{
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
- .dsize = mem_ddr.width/32,
+ .dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
-#ifdef RTT_NOM_120OHM
- .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
-#else
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
-#endif
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
@@ -818,7 +815,7 @@ static void spl_dram_init(void)
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
};
- mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
index ab3bab8..ba15969 100644
--- a/board/gateworks/gw_ventana/eeprom.c
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -81,8 +81,14 @@ read_eeprom(int bus, struct ventana_board_info *info)
type = GW54xx;
break;
case '5':
- type = GW552x;
- break;
+ if (info->model[4] == '1') {
+ type = GW551x;
+ break;
+ } else if (info->model[4] == '2') {
+ type = GW552x;
+ break;
+ }
+ /* fall through */
default:
printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
type = GW_UNKNOWN;
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index a34a9a8..718e165 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -13,8 +13,6 @@
#include "gsc.h"
-#define MINMAX(n, percent) ((n)*(100-percent)/100), ((n)*(100+percent)/100)
-
/*
* The Gateworks System Controller will fail to ACK a master transaction if
* it is busy, which can occur during its 1HZ timer tick while reading ADC's.
@@ -61,9 +59,7 @@ int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
return ret;
}
-#ifdef CONFIG_CMD_GSC
-static void read_hwmon(const char *name, uint reg, uint size, uint low,
- uint high)
+static void read_hwmon(const char *name, uint reg, uint size)
{
unsigned char buf[3];
uint ui;
@@ -75,59 +71,121 @@ static void read_hwmon(const char *name, uint reg, uint size, uint low,
} else {
ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
if (ui == 0xffffff)
- printf("invalid");
- else if (ui < low)
- printf("%d Failed - Low", ui);
- else if (ui > high)
- printf("%d Failed - High", ui);
+ puts("invalid\n");
else
- printf("%d", ui);
+ printf("%d\n", ui);
}
- puts("\n");
}
-int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int gsc_info(int verbose)
{
const char *model = getenv("model");
+ unsigned char buf[16];
i2c_set_bus_num(0);
- read_hwmon("Temp", GSC_HWMON_TEMP, 2, 0, 9000);
- read_hwmon("VIN", GSC_HWMON_VIN, 3, 8000, 60000);
- read_hwmon("VBATT", GSC_HWMON_VBATT, 3, 1800, 3500);
- read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10));
- read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10));
- read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10));
- read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10));
- read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10));
- read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10));
+ if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16))
+ return CMD_RET_FAILURE;
+
+ printf("GSC: v%d", buf[GSC_SC_FWVER]);
+ printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8);
+ printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN))
+ ? "en" : "dis");
+ if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) {
+ buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG);
+ puts(" WDT_RESET");
+ gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
+ &buf[GSC_SC_STATUS], 1);
+ }
+ puts("\n");
+ if (!verbose)
+ return CMD_RET_SUCCESS;
+ read_hwmon("Temp", GSC_HWMON_TEMP, 2);
+ read_hwmon("VIN", GSC_HWMON_VIN, 3);
+ read_hwmon("VBATT", GSC_HWMON_VBATT, 3);
+ read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3);
+ read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3);
+ read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3);
+ read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
+ read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3);
+ read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3);
+ read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3);
+ read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3);
+ read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3);
switch (model[3]) {
case '1': /* GW51xx */
- read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
- read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
+ read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
break;
case '2': /* GW52xx */
+ break;
case '3': /* GW53xx */
- read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
- read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
- read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
+ read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */
+ read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
break;
case '4': /* GW54xx */
- read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10));
- read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10));
- read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
+ read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
+ read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
break;
case '5': /* GW55xx */
- read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
- read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
break;
}
return 0;
}
-U_BOOT_CMD(gsc, 1, 1, do_gsc,
- "GSC test",
- ""
-);
+#ifdef CONFIG_CMD_GSC
+static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned char reg;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (strcasecmp(argv[1], "enable") == 0) {
+ int timeout = 0;
+
+ if (argc > 2)
+ timeout = simple_strtoul(argv[2], NULL, 10);
+ i2c_set_bus_num(0);
+ if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+ return CMD_RET_FAILURE;
+ reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
+ if (timeout == 60)
+ reg |= (1 << GSC_SC_CTRL1_WDTIME);
+ else
+ timeout = 30;
+ reg |= (1 << GSC_SC_CTRL1_WDEN);
+ if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+ return CMD_RET_FAILURE;
+ printf("GSC Watchdog enabled with timeout=%d seconds\n",
+ timeout);
+ } else if (strcasecmp(argv[1], "disable") == 0) {
+ i2c_set_bus_num(0);
+ if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+ return CMD_RET_FAILURE;
+ reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
+ if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+ return CMD_RET_FAILURE;
+ printf("GSC Watchdog disabled\n");
+ } else {
+ return CMD_RET_USAGE;
+ }
+ return CMD_RET_SUCCESS;
+}
+
+static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc < 2)
+ return gsc_info(1);
+
+ if (strcasecmp(argv[1], "wd") == 0)
+ return do_gsc_wd(cmdtp, flag, --argc, ++argv);
+
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ gsc, 4, 1, do_gsc, "GSC configuration",
+ "[wd enable [30|60]]|[wd disable]\n"
+ );
#endif /* CONFIG_CMD_GSC */
diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h
index da970c3..2d4969e 100644
--- a/board/gateworks/gw_ventana/gsc.h
+++ b/board/gateworks/gw_ventana/gsc.h
@@ -19,12 +19,15 @@ enum {
GSC_SC_CTRL0 = 0x00,
GSC_SC_CTRL1 = 0x01,
GSC_SC_STATUS = 0x0a,
+ GSC_SC_FWCRC = 0x0c,
GSC_SC_FWVER = 0x0e,
};
/* System Controller Control1 bits */
enum {
- GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable watchdog */
+ GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */
+ GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */
+ GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */
};
/* System Controller Interrupt bits */
@@ -50,8 +53,10 @@ enum {
GSC_HWMON_VDD_DDR = 0x17,
GSC_HWMON_VDD_SOC = 0x11,
GSC_HWMON_VDD_1P8 = 0x1d,
+ GSC_HWMON_VDD_IO2 = 0x20,
GSC_HWMON_VDD_2P5 = 0x23,
- GSC_HWMON_VDD_1P0 = 0x20,
+ GSC_HWMON_VDD_IO3 = 0x26,
+ GSC_HWMON_VDD_IO4 = 0x29,
};
/*
@@ -60,5 +65,6 @@ enum {
*/
int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len);
int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len);
+int gsc_info(int verbose);
#endif
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index bb08cd2..1e54912 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -89,16 +89,16 @@ DECLARE_GLOBAL_DATA_PTR;
*/
struct ventana_board_info ventana_info;
-int board_type;
+static int board_type;
/* UART1: Function varies per baseboard */
-iomux_v3_cfg_t const uart1_pads[] = {
+static iomux_v3_cfg_t const uart1_pads[] = {
IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
/* UART2: Serial Console */
-iomux_v3_cfg_t const uart2_pads[] = {
+static iomux_v3_cfg_t const uart2_pads[] = {
IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
@@ -106,7 +106,7 @@ iomux_v3_cfg_t const uart2_pads[] = {
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1: GSC */
-struct i2c_pads_info mx6q_i2c_pad_info0 = {
+static struct i2c_pads_info mx6q_i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
@@ -118,7 +118,7 @@ struct i2c_pads_info mx6q_i2c_pad_info0 = {
.gp = IMX_GPIO_NR(3, 28)
}
};
-struct i2c_pads_info mx6dl_i2c_pad_info0 = {
+static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
@@ -132,7 +132,7 @@ struct i2c_pads_info mx6dl_i2c_pad_info0 = {
};
/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
-struct i2c_pads_info mx6q_i2c_pad_info1 = {
+static struct i2c_pads_info mx6q_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
@@ -144,7 +144,7 @@ struct i2c_pads_info mx6q_i2c_pad_info1 = {
.gp = IMX_GPIO_NR(4, 13)
}
};
-struct i2c_pads_info mx6dl_i2c_pad_info1 = {
+static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
@@ -158,7 +158,7 @@ struct i2c_pads_info mx6dl_i2c_pad_info1 = {
};
/* I2C3: Misc/Expansion */
-struct i2c_pads_info mx6q_i2c_pad_info2 = {
+static struct i2c_pads_info mx6q_i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
@@ -170,7 +170,7 @@ struct i2c_pads_info mx6q_i2c_pad_info2 = {
.gp = IMX_GPIO_NR(1, 6)
}
};
-struct i2c_pads_info mx6dl_i2c_pad_info2 = {
+static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
@@ -184,7 +184,7 @@ struct i2c_pads_info mx6dl_i2c_pad_info2 = {
};
/* MMC */
-iomux_v3_cfg_t const usdhc3_pads[] = {
+static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -196,7 +196,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
};
/* ENET */
-iomux_v3_cfg_t const enet_pads[] = {
+static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
@@ -220,7 +220,7 @@ iomux_v3_cfg_t const enet_pads[] = {
};
/* NAND */
-iomux_v3_cfg_t const nfc_pads[] = {
+static iomux_v3_cfg_t const nfc_pads[] = {
IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
@@ -285,7 +285,7 @@ static void setup_iomux_uart(void)
}
#ifdef CONFIG_USB_EHCI_MX6
-iomux_v3_cfg_t const usb_pads[] = {
+static iomux_v3_cfg_t const usb_pads[] = {
IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
/* OTG PWR */
@@ -328,7 +328,7 @@ int board_ehci_power(int port, int on)
#endif /* CONFIG_USB_EHCI_MX6 */
#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
+static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
int board_mmc_getcd(struct mmc *mmc)
{
@@ -397,11 +397,15 @@ int board_phy_config(struct phy_device *phydev)
int board_eth_init(bd_t *bis)
{
- setup_iomux_enet();
-
#ifdef CONFIG_FEC_MXC
- if (board_type != GW552x)
+ if (board_type != GW551x && board_type != GW552x) {
+ setup_iomux_enet();
cpu_eth_init(bis);
+ }
+#endif
+
+#ifdef CONFIG_E1000
+ e1000_initialize(bis);
#endif
#ifdef CONFIG_CI_UDC
@@ -409,6 +413,15 @@ int board_eth_init(bd_t *bis)
usb_eth_initialize(bis);
#endif
+ /* default to the first detected enet dev */
+ if (!getenv("ethprime")) {
+ struct eth_device *dev = eth_get_dev_by_index(0);
+ if (dev) {
+ setenv("ethprime", dev->name);
+ printf("set ethprime to %s\n", getenv("ethprime"));
+ }
+ }
+
return 0;
}
@@ -482,6 +495,48 @@ struct display_info_t const displays[] = {{
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
+} }, {
+ /* DLC700JMG-T-4 */
+ .bus = 0,
+ .addr = 0,
+ .detect = NULL,
+ .enable = enable_lvds,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .mode = {
+ .name = "DLC700JMGT4",
+ .refresh = 60,
+ .xres = 1024, /* 1024x600active pixels */
+ .yres = 600,
+ .pixclock = 15385, /* 64MHz */
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ /* DLC800FIG-T-3 */
+ .bus = 0,
+ .addr = 0,
+ .detect = NULL,
+ .enable = enable_lvds,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .mode = {
+ .name = "DLC800FIGT3",
+ .refresh = 60,
+ .xres = 1024, /* 1024x768 active pixels */
+ .yres = 768,
+ .pixclock = 15385, /* 64MHz */
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);
@@ -614,6 +669,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+ /* PCI_RST# (GW522x) */
+ IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
@@ -658,8 +715,6 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* DIOI2C_DIS# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
- /* PCICK_SSON */
- IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* VID_EN */
@@ -668,6 +723,15 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
};
+static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
+ /* PANLED# */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* PCI_RST# */
+ IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
@@ -709,6 +773,7 @@ struct ventana {
int num_pads;
/* DIO pinmux/val */
struct dio_cfg dio_cfg[4];
+ int num_gpios;
/* various gpios (0 if non-existent) */
int leds[3];
int pcie_rst;
@@ -723,7 +788,7 @@ struct ventana {
int wdis;
};
-struct ventana gpio_cfg[] = {
+static struct ventana gpio_cfg[] = {
/* GW5400proto */
{
.gpio_pads = gw54xx_gpio_pads,
@@ -754,6 +819,7 @@ struct ventana gpio_cfg[] = {
4
},
},
+ .num_gpios = 4,
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 10),
@@ -797,6 +863,7 @@ struct ventana gpio_cfg[] = {
4
},
},
+ .num_gpios = 4,
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 10),
@@ -839,6 +906,7 @@ struct ventana gpio_cfg[] = {
0
},
},
+ .num_gpios = 4,
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
@@ -883,6 +951,7 @@ struct ventana gpio_cfg[] = {
0
},
},
+ .num_gpios = 4,
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
@@ -926,6 +995,7 @@ struct ventana gpio_cfg[] = {
4
},
},
+ .num_gpios = 4,
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
@@ -941,10 +1011,10 @@ struct ventana gpio_cfg[] = {
.wdis = IMX_GPIO_NR(5, 17),
},
- /* GW552x */
+ /* GW551x */
{
- .gpio_pads = gw552x_gpio_pads,
- .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
+ .gpio_pads = gw551x_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
.dio_cfg = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
@@ -965,18 +1035,46 @@ struct ventana gpio_cfg[] = {
3
},
{
- { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
- IMX_GPIO_NR(2, 10),
- { 0, 0 },
- 0
+ { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
+ IMX_GPIO_NR(1, 18),
+ { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
+ 4
+ },
+ },
+ .num_gpios = 2,
+ .leds = {
+ IMX_GPIO_NR(4, 7),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 0),
+ .wdis = IMX_GPIO_NR(7, 12),
+ },
+
+ /* GW552x */
+ {
+ .gpio_pads = gw552x_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
+ .dio_cfg = {
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
},
},
+ .num_gpios = 4,
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 29),
+ .wdis = IMX_GPIO_NR(7, 12),
},
};
@@ -1014,22 +1112,32 @@ int power_init_board(void)
p = pmic_get("LTC3676_PMIC");
if (p && !pmic_probe(p)) {
puts("PMIC: LTC3676\n");
- /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
- if (is_cpu_type(MXC_CPU_MX6Q)) {
- /* mask PGOOD during SW1 transition */
- reg = 0x1d | LTC3676_PGOOD_MASK;
- pmic_reg_write(p, LTC3676_DVB1B, reg);
- /* set SW1 (VDD_SOC) to 1259mV */
- reg = 0x1d;
- pmic_reg_write(p, LTC3676_DVB1A, reg);
-
- /* mask PGOOD during SW3 transition */
- reg = 0x1d | LTC3676_PGOOD_MASK;
- pmic_reg_write(p, LTC3676_DVB3B, reg);
- /*set SW3 (VDD_ARM) to 1259mV */
- reg = 0x1d;
- pmic_reg_write(p, LTC3676_DVB3A, reg);
- }
+ /*
+ * set board-specific scalar for max CPU frequency
+ * per CPU based on the LDO enabled Operating Ranges
+ * defined in the respective IMX6DQ and IMX6SDL
+ * datasheets. The voltage resulting from the R1/R2
+ * feedback inputs on Ventana is 1308mV. Note that this
+ * is a bit shy of the Vmin of 1350mV in the datasheet
+ * for LDO enabled mode but is as high as we can go.
+ *
+ * We will rely on an OS kernel driver to properly
+ * regulate these per CPU operating point and use LDO
+ * bypass mode when using the higher frequency
+ * operating points to compensate as LDO bypass mode
+ * allows the rails be 125mV lower.
+ */
+ /* mask PGOOD during SW1 transition */
+ pmic_reg_write(p, LTC3676_DVB1B,
+ 0x1f | LTC3676_PGOOD_MASK);
+ /* set SW1 (VDD_SOC) */
+ pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
+
+ /* mask PGOOD during SW3 transition */
+ pmic_reg_write(p, LTC3676_DVB3B,
+ 0x1f | LTC3676_PGOOD_MASK);
+ /* set SW3 (VDD_ARM) */
+ pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
}
}
@@ -1062,6 +1170,10 @@ static void setup_board_gpio(int board)
}
#if !defined(CONFIG_CMD_PCI)
+ /* GW522x Uses GPIO3_IO23 for PCIE_RST# */
+ if (board_type == GW52xx && info->model[4] == '2')
+ gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23);
+
/* assert PCI_RST# (released by OS when clock is valid) */
gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
#endif
@@ -1100,7 +1212,9 @@ static void setup_board_gpio(int board)
/* USBOTG Select (PCISKT or FrontPanel) */
if (gpio_cfg[board].usb_sel)
- gpio_direction_output(gpio_cfg[board].usb_sel, 0);
+ gpio_direction_output(gpio_cfg[board].usb_sel,
+ (hwconfig("usb_pcisel")) ? 1 : 0);
+
/* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
if (gpio_cfg[board].wdis)
@@ -1115,6 +1229,8 @@ static void setup_board_gpio(int board)
iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
+ if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
+ continue;
sprintf(arg, "dio%d", i);
if (!hwconfig(arg))
continue;
@@ -1320,15 +1436,8 @@ int checkboard(void)
return 0;
/* Display GSC firmware revision/CRC/status */
- i2c_set_bus_num(CONFIG_I2C_GSC);
- if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
- printf("GSC: v%d", buf[0]);
- if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
- printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
- printf(" 0x%02x", buf[0]); /* irq status */
- }
- puts("\n");
- }
+ gsc_info(0);
+
/* Display RTC */
if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
printf("RTC: %d\n",
@@ -1407,7 +1516,7 @@ int misc_init_r(void)
sprintf(fdt, "%s-%s.dtb", cputype, str);
setenv("fdt_file1", fdt);
}
- if (board_type != GW552x)
+ if (board_type != GW551x && board_type != GW552x)
str[4] = 'x';
str[5] = 'x';
str[6] = 0;
@@ -1430,6 +1539,10 @@ int misc_init_r(void)
/* board serial-number */
sprintf(str, "%6d", info->serial);
setenv("serial#", str);
+
+ /* memory MB */
+ sprintf(str, "%d", (int) (gd->ram_size >> 20));
+ setenv("mem_mb", str);
}
@@ -1461,19 +1574,48 @@ int misc_init_r(void)
} else {
puts("Error: could not disable GSC Watchdog\n");
}
- if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
- if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
- puts("GSC boot watchdog timeout detected\n");
- reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
- gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
- }
- }
return 0;
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+static int ft_sethdmiinfmt(void *blob, char *mode)
+{
+ int off;
+
+ if (!mode)
+ return -EINVAL;
+
+ off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
+ if (off < 0)
+ return off;
+
+ if (0 == strcasecmp(mode, "yuv422bt656")) {
+ u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
+ 0x00, 0x00, 0x00 };
+ mode = "422_ccir";
+ fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
+ fdt_setprop_u32(blob, off, "vidout_trc", 1);
+ fdt_setprop_u32(blob, off, "vidout_blc", 1);
+ fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
+ printf(" set HDMI input mode to %s\n", mode);
+ } else if (0 == strcasecmp(mode, "yuv422smp")) {
+ u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
+ 0x82, 0x81, 0x00 };
+ mode = "422_smp";
+ fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
+ fdt_setprop_u32(blob, off, "vidout_trc", 0);
+ fdt_setprop_u32(blob, off, "vidout_blc", 0);
+ fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
+ printf(" set HDMI input mode to %s\n", mode);
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
/*
* called prior to booting kernel or by 'fdt boardsetup' command
*
@@ -1492,6 +1634,17 @@ int ft_board_setup(void *blob, bd_t *bd)
{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
};
const char *model = getenv("model");
+ const char *display = getenv("display");
+ int i;
+ char rev = 0;
+
+ /* determine board revision */
+ for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
+ if (ventana_info.model[i] >= 'A') {
+ rev = ventana_info.model[i];
+ break;
+ }
+ }
if (getenv("fdt_noauto")) {
puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
@@ -1502,6 +1655,13 @@ int ft_board_setup(void *blob, bd_t *bd)
puts(" Updating MTD partitions...\n");
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ /* Update display timings from display env var */
+ if (display) {
+ if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
+ display) >= 0)
+ printf(" Set display timings for %s...\n", display);
+ }
+
if (!model) {
puts("invalid board info: Leaving FDT fully enabled\n");
return 0;
@@ -1516,6 +1676,91 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_setprop(blob, 0, "board", info->model,
strlen((const char *)info->model) + 1);
+ /* set desired digital video capture format */
+ ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
+
+ /*
+ * disable serial2 node for GW54xx for compatibility with older
+ * 3.10.x kernel that improperly had this node enabled in the DT
+ */
+ if (board_type == GW54xx) {
+ i = fdt_path_offset(blob,
+ "/soc/aips-bus@02100000/serial@021ec000");
+ if (i)
+ fdt_del_node(blob, i);
+ }
+
+ /*
+ * disable wdog1/wdog2 nodes for GW51xx below revC to work around
+ * errata causing wdog timer to be unreliable.
+ */
+ if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
+ i = fdt_path_offset(blob,
+ "/soc/aips-bus@02000000/wdog@020bc000");
+ if (i)
+ fdt_status_disabled(blob, i);
+ }
+
+ /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
+ else if (board_type == GW52xx && info->model[4] == '2') {
+ u32 handle = 0;
+ u32 *range = NULL;
+
+ i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
+ if (i)
+ range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
+ NULL);
+
+ if (range) {
+ i = fdt_path_offset(blob,
+ "/soc/aips-bus@02000000/gpio@020a4000");
+ if (i)
+ handle = fdt_get_phandle(blob, i);
+ if (handle) {
+ range[0] = cpu_to_fdt32(handle);
+ range[1] = cpu_to_fdt32(23);
+ }
+ }
+ }
+
+ /*
+ * isolate CSI0_DATA_EN for GW551x below revB to work around
+ * errata causing non functional digital video in (it is not hooked up)
+ */
+ else if (board_type == GW551x && rev == 'A') {
+ u32 *range = NULL;
+ int len;
+ const u32 *handle = NULL;
+
+ i = fdt_node_offset_by_compatible(blob, -1,
+ "fsl,imx-tda1997x-video");
+ if (i)
+ handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
+ if (handle)
+ i = fdt_node_offset_by_phandle(blob,
+ fdt32_to_cpu(*handle));
+ if (i)
+ range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
+ if (range) {
+ len /= sizeof(u32);
+ for (i = 0; i < len; i += 6) {
+ u32 mux_reg = fdt32_to_cpu(range[i+0]);
+ u32 conf_reg = fdt32_to_cpu(range[i+1]);
+ /* mux PAD_CSI0_DATA_EN to GPIO */
+ if (is_cpu_type(MXC_CPU_MX6Q) &&
+ mux_reg == 0x260 && conf_reg == 0x630)
+ range[i+3] = cpu_to_fdt32(0x5);
+ else if (!is_cpu_type(MXC_CPU_MX6Q) &&
+ mux_reg == 0x08c && conf_reg == 0x3a0)
+ range[i+3] = cpu_to_fdt32(0x5);
+ }
+ fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
+ }
+
+ /* set BT656 video format */
+ ft_sethdmiinfmt(blob, "yuv422bt656");
+ }
+
/*
* Peripheral Config:
* remove nodes by alias path if EEPROM config tells us the
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index 9712812..0c0fee3 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -188,7 +188,21 @@ struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
.grp_b7ds = 0x00000030,
};
-/* MT41K128M16JT-125 */
+/* MT41K64M16JT-125 (1Gb density) */
+static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
+ .mem_speed = 1600,
+ .density = 1,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 13,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/* MT41K128M16JT-125 (2Gb density) */
static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
.mem_speed = 1600,
.density = 2,
@@ -202,7 +216,7 @@ static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
.trasmin = 3500,
};
-/* MT41K256M16HA-125 */
+/* MT41K256M16HA-125 (4Gb density) */
static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
.mem_speed = 1600,
.density = 4,
@@ -219,6 +233,44 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
/*
* calibration - these are the various CPU/DDR3 combinations we support
*/
+static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x004C004E,
+ .p0_mpwldectrl1 = 0x00440044,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x42440247,
+ .p0_mpdgctrl1 = 0x02310232,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x45424746,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x33382C31,
+};
+
+static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x001B0016,
+ .p0_mpwldectrl1 = 0x000C000E,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x4324033A,
+ .p0_mpdgctrl1 = 0x00000000,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x40403438,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x40403D36,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00420043,
+ .p0_mpwldectrl1 = 0x0016001A,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x4238023B,
+ .p0_mpdgctrl1 = 0x00000000,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x40404849,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x40402E2F,
+};
static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
/* write leveling calibration determine */
@@ -297,6 +349,19 @@ static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
.p0_mpwrdlctl = 0x32363934,
};
+static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0X00480047,
+ .p0_mpwldectrl1 = 0X003D003F,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0X423E0241,
+ .p0_mpdgctrl1 = 0X022B022C,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0X49454A4A,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0X2E372C32,
+};
+
static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0X00220021,
@@ -340,6 +405,7 @@ static void spl_dram_init(int width, int size_mb, int board_model)
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .pd_fast_exit = 1, /* enable precharge power-down fast exit */
};
/*
@@ -349,25 +415,60 @@ static void spl_dram_init(int width, int size_mb, int board_model)
* mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
* mx6_ddr_cfg - chip specific timing/layout details
*/
- if (width == 32 && size_mb == 512) {
+ if (width == 16 && size_mb == 128) {
+ mem = &mt41k64m16jt_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ ;
+ else
+ calib = &mx6sdl_64x16_mmdc_calib;
+ debug("1gB density\n");
+ } else if (width == 16 && size_mb == 256) {
+ /* 1x 2Gb density chip - same calib as 2x 2Gb */
mem = &mt41k128m16jt_125;
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_128x32_mmdc_calib;
else
calib = &mx6sdl_128x32_mmdc_calib;
debug("2gB density\n");
- } else if (width == 64 && size_mb == 1024) {
+ } else if (width == 16 && size_mb == 512) {
+ mem = &mt41k256m16ha_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_256x16_mmdc_calib;
+ else
+ calib = &mx6sdl_256x16_mmdc_calib;
+ debug("4gB density\n");
+ } else if (width == 32 && size_mb == 256) {
+ /* Same calib as width==16, size==128 */
+ mem = &mt41k64m16jt_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ ;
+ else
+ calib = &mx6sdl_64x16_mmdc_calib;
+ debug("1gB density\n");
+ } else if (width == 32 && size_mb == 512) {
mem = &mt41k128m16jt_125;
if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &mx6dq_128x64_mmdc_calib;
+ calib = &mx6dq_128x32_mmdc_calib;
else
- calib = &mx6sdl_128x64_mmdc_calib;
+ calib = &mx6sdl_128x32_mmdc_calib;
debug("2gB density\n");
- } else if (width == 32 && size_mb == 1024) {
+ } else if (width == 32 && size_mb == 1024) {
mem = &mt41k256m16ha_125;
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_256x32_mmdc_calib;
+ else
+ calib = &mx6sdl_256x32_mmdc_calib;
debug("4gB density\n");
+ } else if (width == 64 && size_mb == 512) {
+ mem = &mt41k64m16jt_125;
+ debug("1gB density\n");
+ } else if (width == 64 && size_mb == 1024) {
+ mem = &mt41k128m16jt_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_128x64_mmdc_calib;
+ else
+ calib = &mx6sdl_128x64_mmdc_calib;
+ debug("2gB density\n");
} else if (width == 64 && size_mb == 2048) {
mem = &mt41k256m16ha_125;
if (is_cpu_type(MXC_CPU_MX6Q))
@@ -375,12 +476,14 @@ static void spl_dram_init(int width, int size_mb, int board_model)
debug("4gB density\n");
}
- if (!mem) {
- puts("Error: Invalid Memory Configuration\n");
- hang();
- }
- if (!calib) {
- puts("Error: Invalid Board Calibration Configuration\n");
+ if (!(mem && calib)) {
+ puts("Error: Invalid Calibration/Board Configuration\n");
+ printf("MEM : %s\n", mem ? "OKAY" : "NULL");
+ printf("CALIB : %s\n", calib ? "OKAY" : "NULL");
+ printf("CPUTYPE: %s\n",
+ is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
+ printf("SIZE_MB: %d\n", size_mb);
+ printf("WIDTH : %d\n", width);
hang();
}
diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h
index af12711..daff375 100644
--- a/board/gateworks/gw_ventana/ventana_eeprom.h
+++ b/board/gateworks/gw_ventana/ventana_eeprom.h
@@ -109,6 +109,7 @@ enum {
GW52xx,
GW53xx,
GW54xx,
+ GW551x,
GW552x,
GW_UNKNOWN,
GW_BADCRC,
diff --git a/board/solidrun/mx6cuboxi/Kconfig b/board/solidrun/mx6cuboxi/Kconfig
new file mode 100644
index 0000000..31d88b2
--- /dev/null
+++ b/board/solidrun/mx6cuboxi/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX6CUBOXI
+
+config SYS_BOARD
+ default "mx6cuboxi"
+
+config SYS_VENDOR
+ default "solidrun"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "mx6cuboxi"
+
+endif
diff --git a/board/solidrun/mx6cuboxi/MAINTAINERS b/board/solidrun/mx6cuboxi/MAINTAINERS
new file mode 100644
index 0000000..a3506c2
--- /dev/null
+++ b/board/solidrun/mx6cuboxi/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6CUBOXI BOARD
+M: Fabio Estevam <fabio.estevam@freescale.com>
+S: Maintained
+F: board/solidrun/mx6cuboxi/
+F: include/configs/mx6cuboxi.h
+F: configs/mx6cuboxi_defconfig
diff --git a/board/solidrun/mx6cuboxi/Makefile b/board/solidrun/mx6cuboxi/Makefile
new file mode 100644
index 0000000..df425ac
--- /dev/null
+++ b/board/solidrun/mx6cuboxi/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6cuboxi.o
diff --git a/board/solidrun/mx6cuboxi/README b/board/solidrun/mx6cuboxi/README
new file mode 100644
index 0000000..3050c48
--- /dev/null
+++ b/board/solidrun/mx6cuboxi/README
@@ -0,0 +1,21 @@
+How to use U-boot on Solid-run mx6 hummingboard
+-----------------------------------------------
+
+- Build U-boot for hummingboard:
+
+$ make mrproper
+$ make mx6cuboxi_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Insert the SD card in the hummingboard, power it up and U-boot messages
+should come up.
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
new file mode 100644
index 0000000..d3a32c1
--- /dev/null
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -0,0 +1,510 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * Based on SPL code from Solidrun tree, which is:
+ * Author: Tungyi Lin <tungyilin1127@gmail.com>
+ *
+ * Derived from EDM_CF_IMX6 code by TechNexion,Inc
+ * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const hb_cbi_sense[] = {
+ /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
+ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+ SETUP_IOMUX_PADS(uart1_pads);
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1; /* uSDHC2 is always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ /* AR8035 reset */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
+ /* AR8035 interrupt */
+ IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ /* GPIO16 -> AR8035 25MHz */
+ IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
+};
+
+static void setup_iomux_enet(void)
+{
+ SETUP_IOMUX_PADS(enet_pads);
+
+ gpio_direction_output(ETH_PHY_RESET, 0);
+ mdelay(2);
+ gpio_set_value(ETH_PHY_RESET, 1);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ int ret = enable_fec_anatop_clock(ENET_25MHZ);
+ if (ret)
+ return ret;
+
+ /* set gpr1[ENET_CLK_SEL] */
+ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+ setup_iomux_enet();
+
+ return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+static bool is_hummingboard(void)
+{
+ int val1, val2;
+
+ SETUP_IOMUX_PADS(hb_cbi_sense);
+
+ gpio_direction_input(IMX_GPIO_NR(4, 9));
+ gpio_direction_input(IMX_GPIO_NR(3, 4));
+
+ val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
+ val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
+
+ /*
+ * Machine selection -
+ * Machine val1, val2
+ * -------------------------
+ * HB rev 3.x x 0
+ * CBi 0 1
+ * HB 1 1
+ */
+
+ if (val2 == 0)
+ return true;
+ else if (val1 == 0)
+ return false;
+ else
+ return true;
+}
+
+int checkboard(void)
+{
+ if (is_hummingboard())
+ puts("Board: MX6 Hummingboard\n");
+ else
+ puts("Board: MX6 Cubox-i\n");
+
+ return 0;
+}
+
+static bool is_mx6q(void)
+{
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ return true;
+ else
+ return false;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if (is_hummingboard())
+ setenv("board_name", "HUMMINGBOARD");
+ else
+ setenv("board_name", "CUBOXI");
+
+ if (is_mx6q())
+ setenv("board_rev", "MX6Q");
+ else
+ setenv("board_rev", "MX6DL");
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <asm/arch/mx6-ddr.h>
+static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
+ .dram_sdclk_0 = 0x00020030,
+ .dram_sdclk_1 = 0x00020030,
+ .dram_cas = 0x00020030,
+ .dram_ras = 0x00020030,
+ .dram_reset = 0x00020030,
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x00003030,
+ .dram_sdodt1 = 0x00003030,
+ .dram_sdqs0 = 0x00000030,
+ .dram_sdqs1 = 0x00000030,
+ .dram_sdqs2 = 0x00000030,
+ .dram_sdqs3 = 0x00000030,
+ .dram_sdqs4 = 0x00000030,
+ .dram_sdqs5 = 0x00000030,
+ .dram_sdqs6 = 0x00000030,
+ .dram_sdqs7 = 0x00000030,
+ .dram_dqm0 = 0x00020030,
+ .dram_dqm1 = 0x00020030,
+ .dram_dqm2 = 0x00020030,
+ .dram_dqm3 = 0x00020030,
+ .dram_dqm4 = 0x00020030,
+ .dram_dqm5 = 0x00020030,
+ .dram_dqm6 = 0x00020030,
+ .dram_dqm7 = 0x00020030,
+};
+
+static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
+ .dram_sdclk_0 = 0x00000028,
+ .dram_sdclk_1 = 0x00000028,
+ .dram_cas = 0x00000028,
+ .dram_ras = 0x00000028,
+ .dram_reset = 0x000c0028,
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x00003030,
+ .dram_sdodt1 = 0x00003030,
+ .dram_sdqs0 = 0x00000028,
+ .dram_sdqs1 = 0x00000028,
+ .dram_sdqs2 = 0x00000028,
+ .dram_sdqs3 = 0x00000028,
+ .dram_sdqs4 = 0x00000028,
+ .dram_sdqs5 = 0x00000028,
+ .dram_sdqs6 = 0x00000028,
+ .dram_sdqs7 = 0x00000028,
+ .dram_dqm0 = 0x00000028,
+ .dram_dqm1 = 0x00000028,
+ .dram_dqm2 = 0x00000028,
+ .dram_dqm3 = 0x00000028,
+ .dram_dqm4 = 0x00000028,
+ .dram_dqm5 = 0x00000028,
+ .dram_dqm6 = 0x00000028,
+ .dram_dqm7 = 0x00000028,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
+ .grp_ddr_type = 0x000C0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_b2ds = 0x00000030,
+ .grp_b3ds = 0x00000030,
+ .grp_b4ds = 0x00000030,
+ .grp_b5ds = 0x00000030,
+ .grp_b6ds = 0x00000030,
+ .grp_b7ds = 0x00000030,
+};
+
+static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = 0x00000028,
+ .grp_ctlds = 0x00000028,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000028,
+ .grp_b1ds = 0x00000028,
+ .grp_b2ds = 0x00000028,
+ .grp_b3ds = 0x00000028,
+ .grp_b4ds = 0x00000028,
+ .grp_b5ds = 0x00000028,
+ .grp_b6ds = 0x00000028,
+ .grp_b7ds = 0x00000028,
+};
+
+/* microSOM with Dual processor and 1GB memory */
+static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpwldectrl1 = 0x00000000,
+ .p1_mpwldectrl0 = 0x00000000,
+ .p1_mpwldectrl1 = 0x00000000,
+ .p0_mpdgctrl0 = 0x0314031c,
+ .p0_mpdgctrl1 = 0x023e0304,
+ .p1_mpdgctrl0 = 0x03240330,
+ .p1_mpdgctrl1 = 0x03180260,
+ .p0_mprddlctl = 0x3630323c,
+ .p1_mprddlctl = 0x3436283a,
+ .p0_mpwrdlctl = 0x36344038,
+ .p1_mpwrdlctl = 0x422a423c,
+};
+
+/* microSOM with Quad processor and 2GB memory */
+static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpwldectrl1 = 0x00000000,
+ .p1_mpwldectrl0 = 0x00000000,
+ .p1_mpwldectrl1 = 0x00000000,
+ .p0_mpdgctrl0 = 0x0314031c,
+ .p0_mpdgctrl1 = 0x023e0304,
+ .p1_mpdgctrl0 = 0x03240330,
+ .p1_mpdgctrl1 = 0x03180260,
+ .p0_mprddlctl = 0x3630323c,
+ .p1_mprddlctl = 0x3436283a,
+ .p0_mpwrdlctl = 0x36344038,
+ .p1_mpwrdlctl = 0x422a423c,
+};
+
+/* microSOM with Solo processor and 512MB memory */
+static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x0045004D,
+ .p0_mpwldectrl1 = 0x003A0047,
+ .p0_mpdgctrl0 = 0x023C0224,
+ .p0_mpdgctrl1 = 0x02000220,
+ .p0_mprddlctl = 0x44444846,
+ .p0_mpwrdlctl = 0x32343032,
+};
+
+/* microSOM with Dual lite processor and 1GB memory */
+static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x0045004D,
+ .p0_mpwldectrl1 = 0x003A0047,
+ .p1_mpwldectrl0 = 0x001F001F,
+ .p1_mpwldectrl1 = 0x00210035,
+ .p0_mpdgctrl0 = 0x023C0224,
+ .p0_mpdgctrl1 = 0x02000220,
+ .p1_mpdgctrl0 = 0x02200220,
+ .p1_mpdgctrl1 = 0x02000220,
+ .p0_mprddlctl = 0x44444846,
+ .p1_mprddlctl = 0x4042463C,
+ .p0_mpwrdlctl = 0x32343032,
+ .p1_mpwrdlctl = 0x36363430,
+};
+
+static struct mx6_ddr3_cfg mem_ddr_2g = {
+ .mem_speed = 1600,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+ .SRT = 1,
+};
+
+static struct mx6_ddr3_cfg mem_ddr_4g = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+/*
+ * This section requires the differentiation between Solidrun mx6 boards, but
+ * for now, it will configure only for the mx6dual hummingboard version.
+ */
+static void spl_dram_init(int width)
+{
+ struct mx6_ddr_sysinfo sysinfo = {
+ /* width of data bus: 0=16, 1=32, 2=64 */
+ .dsize = width / 32,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32, /* 32Gb per CS */
+ .ncs = 1, /* single chip select */
+ .cs1_mirror = 0,
+ .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
+ .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ };
+
+ if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q))
+ mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
+ else
+ mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
+
+ if (is_cpu_type(MXC_CPU_MX6D))
+ mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
+ else if (is_cpu_type(MXC_CPU_MX6Q))
+ mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
+ else if (is_cpu_type(MXC_CPU_MX6DL))
+ mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
+ else if (is_cpu_type(MXC_CPU_MX6SOLO))
+ mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ if (is_cpu_type(MXC_CPU_MX6SOLO))
+ spl_dram_init(32);
+ else
+ spl_dram_init(64);
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif