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| author | Stefano Babic <sbabic@denx.de> | 2016-06-18 10:24:54 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-06-18 10:25:13 +0200 |
| commit | dc557e9a1fe00ca9d884bd88feef5bebf23fede4 (patch) | |
| tree | ec09fdf8f7c4c44e30f4b38b7459a2cbbb71d094 /board | |
| parent | d2ba7a6adcef6e6f8c4418c7b0caf9d7ab98a6d4 (diff) | |
| parent | 6b3943f1b04be60f147ee540fbd72c4c7ea89f80 (diff) | |
| download | u-boot-imx-dc557e9a1fe00ca9d884bd88feef5bebf23fede4.zip u-boot-imx-dc557e9a1fe00ca9d884bd88feef5bebf23fede4.tar.gz u-boot-imx-dc557e9a1fe00ca9d884bd88feef5bebf23fede4.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board')
258 files changed, 6106 insertions, 3776 deletions
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index ce4acc1..e947e54 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -259,7 +259,7 @@ static int load_devicetree(void) } #ifdef CONFIG_NAND dtbsize = 0x20000; - rc = nand_read_skip_bad(&nand_info[0], 0x40000, (size_t *)&dtbsize, + rc = nand_read_skip_bad(nand_info[0], 0x40000, (size_t *)&dtbsize, NULL, 0x20000, (u_char *)dtbaddr); #else char *dtbname = getenv("dtb"); diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt deleted file mode 100644 index 6cae9ea..0000000 --- a/board/Marvell/common/bootseq.txt +++ /dev/null @@ -1,94 +0,0 @@ -(cpu/mpc7xxx/start.S) - -start: - b boot_cold - -start_warm: - b boot_warm - - -boot_cold: -boot_warm: - clear bats - init l2 (if enabled) - init altivec (if enabled) - invalidate l2 (if enabled) - setup bats (from defines in config_EVB) - enable_addr_trans: (if MMU enabled) - enable MSR_IR and MSR_DR - jump to in_flash - -in_flash: - enable l1 dcache - gal_low_init: (board/evb64260/sdram_init.S) - config SDRAM (CFG, TIMING, DECODE) - init scratch regs (810 + 814) - - detect DIMM0 (bank 0 only) - config SDRAM_PARA0 to 256/512Mbit - bl sdram_op_mode - detect bank0 width - write scratch reg 810 - config SDRAM_PARA0 with results - config SDRAM_PARA1 with results - - detect DIMM1 (bank 2 only) - config SDRAM_PARA2 to 256/512Mbit - detect bank2 width - write scratch reg 814 - config SDRAM_PARA2 with results - config SDRAM_PARA3 with results - - setup device bus timings/width - setup boot device timings/width - - setup CPU_CONF (0x0) - setup cpu master control register 0x160 - setup PCI0 TIMEOUT - setup PCI1 TIMEOUT - setup PCI0 BAR - setup PCI1 BAR - - setup MPP control 0-3 - setup GPP level control - setup Serial ports multiplex - - setup stack pointer (r1) - setup GOT - call cpu_init_f - debug leds - board_init_f: (common/board.c) - board_early_init_f: - remap gt regs? - map PCI mem/io - map device space - clear out interrupts - init_timebase - env_init - serial_init - console_init_f - display_options - initdram: (board/evb64260/evb64260.c) - detect memory - for each bank: - dram_size() - setup PCI slave memory mappings - setup SCS - setup monitor - alloc board info struct - init bd struct - relocate_code: (cpu/mpc7xxx/start.S) - copy,got,clearbss - board_init_r(bd, dest_addr) (common/board.c) - setup bd function pointers - trap_init - flash_init: (board/evb64260/flash.c) - setup bd flash info - cpu_init_r: (cpu/mpc7xxx/cpu_init.c) - nothing - mem_malloc_init - malloc_bin_reloc - spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM) - env_relocated - misc_init_r(bd): (board/evb64260/evb64260.c) - mpsc_init2 diff --git a/board/Marvell/common/i2c.h b/board/Marvell/common/i2c.h deleted file mode 100644 index a879ea9..0000000 --- a/board/Marvell/common/i2c.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the DB64360 board by Ingo.Assmus@keymile.com - */ - -#ifndef __I2C_H__ -#define __I2C_H__ - -/* function declarations */ -uchar i2c_read(uchar, unsigned int, int, uchar*, int); - -#endif diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h deleted file mode 100644 index 5531f95..0000000 --- a/board/Marvell/common/intel_flash.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the marvell db64360 eval board by - * Ingo Assmus <ingo.assmus@keymile.com> - */ - -/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ - -/* - * acceptable chips types are: - * - * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A - */ - -/* register addresses, valid only following an CHIP_CMD_RD_ID command */ -#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */ -#define CHIP_ADDR_REG_DEV 0x000001 /* device id */ -#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */ -#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */ - -/* Commands */ -#define CHIP_CMD_RST 0xFF /* reset flash */ -#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */ -#define CHIP_CMD_RD_STAT 0x70 /* read the status register */ -#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */ -#define CHIP_CMD_PROG 0x40 /* program word command */ -#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */ -#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */ -#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ -#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */ -#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ -#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ -#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ - -/* status register bits */ -#define CHIP_STAT_DPS 0x02 /* Device Protect Status */ -#define CHIP_STAT_VPPS 0x08 /* VPP Status */ -#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ -#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ -#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */ -#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ - -#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \ - CHIP_STAT_ECLBS | CHIP_STAT_PSLBS) - -/* ID and Lock Configuration */ -#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ -#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID - -/* dimensions */ -#define CHIP_WIDTH 2 /* chips are in 16 bit mode */ -#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */ -#define CHIP_NBLOCKS 128 -#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */ -#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS) - -/********************** DEFINES for Hymod Flash ******************************/ - -/* - * The hymod board has 2 x 28F320J5 chips running in - * 16 bit mode, for a 32 bit wide bank. - */ - -typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */ -typedef volatile bank_word_t *bank_addr_t; -typedef unsigned long bank_size_t; /* want this big - >= 32 bit */ - -#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */ -#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */ - -#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH) -#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT) -#define BANK_NBLOCKS CHIP_NBLOCKS -#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH) -#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH) - -#define MAX_BANKS 1 /* only one bank possible */ - -/* align bank addresses and sizes to bank word boundaries */ -#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_WIDTH - 1))) -#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \ - (bank_size_t)(s) + (BANK_WIDTH - 1))) - -/* align bank addresses and sizes to bank block boundaries */ -#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_BLKSZ - 1))) -#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \ - (bank_size_t)(s) + (BANK_BLKSZ - 1))) - -/* align bank addresses and sizes to bank boundaries */ -#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_SIZE - 1))) -#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \ - (bank_size_t)(s) + (BANK_SIZE - 1))) - -/* add an offset to a bank address */ -#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \ - (bank_size_t)(o)) - -/* get base address of bank b, given flash base address a */ -#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - (bank_size_t)(b) * BANK_SIZE) - -/* adjust a bank address to start of next word, block or bank */ -#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ - BANK_WIDTH) -#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ - BANK_BLKSZ) -#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - BANK_SIZE) - -/* get bank address of chip register r given a bank base address a */ -#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - ((bank_size_t)(r) << BANK_WSHIFT)) - -/* make a bank address for each chip register address */ - -#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN) -#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV) -#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM) -#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b)) - -/* - * replicate a chip cmd/stat/rd value into each byte position within a word - * so that multiple chips are accessed in a single word i/o operation - * - * this must be as wide as the bank_word_t type, and take into account the - * chip width and bank layout - */ - -#define BANK_FILL_WORD(o) ((bank_word_t)(o)) - -/* make a bank word value for each chip cmd/stat/rd value */ - -/* Commands */ -#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST) -#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID) -#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT) -#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT) -#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1) -#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2) -#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG) -#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK) -#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK) -#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR) -#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS) -#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS) -#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS) -#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS) -#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS) -#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS) -#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY) - -#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR) - -/* ID and Lock Configuration */ -#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK) -#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN) -#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV) diff --git a/board/Marvell/common/memory.c b/board/Marvell/common/memory.c deleted file mode 100644 index 610b411..0000000 --- a/board/Marvell/common/memory.c +++ /dev/null @@ -1,1374 +0,0 @@ -/* - * Copyright - Galileo technology. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * - * written or collected and sometimes rewritten by - * Ingo Assmus <ingo.assmus@keymile.com> - * - */ - - -#include <common.h> -#include "../include/core.h" -#include "../include/memory.h" - -/******************************************************************************* -* memoryGetBankBaseAddress - Returns the base address of a memory bank. -* DESCRIPTION: -* This function returns the base address of one of the SDRAM's memory -* banks. There are 4 memory banks and each one represents one DIMM side. -* INPUT: -* MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h. -* OUTPUT: -* None. -* RETURN: -* 32 bit Memory bank base address. -*******************************************************************************/ -static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank) -{ - switch (bank) { - case BANK0: - return SCS_0_LOW_DECODE_ADDRESS; - case BANK1: - return SCS_1_LOW_DECODE_ADDRESS; - case BANK2: - return SCS_2_LOW_DECODE_ADDRESS; - case BANK3: - return SCS_3_LOW_DECODE_ADDRESS; - - } - return SCS_0_LOW_DECODE_ADDRESS; /* default value */ -} - -unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank) -{ - unsigned int base; - unsigned int regOffset = memoryGetBankRegOffset (bank); - - GT_REG_READ (regOffset, &base); - base = base << 16; /* MV6436x */ - return base; -} - -/******************************************************************************* -* memoryGetDeviceBaseAddress - Returns the base address of a device. -* DESCRIPTION: -* This function returns the base address of a device on the system. There -* are 5 possible devices (0 - 4 and one boot device) as defined in -* gtMemory.h. Each of the device parameters is maped to one of the CS -* (Devices chip selects) base address register. -* INPUT: -* device - Selects one of the five devices as defined in Memory.h. -* OUTPUT: -* None. -* RETURN: -* 32 bit Device base address. -* -*******************************************************************************/ -static unsigned int memoryGetDeviceRegOffset (DEVICE device) -{ - switch (device) { - case DEVICE0: - return CS_0_LOW_DECODE_ADDRESS; - case DEVICE1: - return CS_1_LOW_DECODE_ADDRESS; - case DEVICE2: - return CS_2_LOW_DECODE_ADDRESS; - case DEVICE3: - return CS_3_LOW_DECODE_ADDRESS; - case BOOT_DEVICE: - return BOOTCS_LOW_DECODE_ADDRESS; - } - return CS_0_LOW_DECODE_ADDRESS; /* default value */ -} - -unsigned int memoryGetDeviceBaseAddress (DEVICE device) -{ - unsigned int regBase; - unsigned int regOffset = memoryGetDeviceRegOffset (device); - - GT_REG_READ (regOffset, ®Base); - - regBase = regBase << 16; /* MV6436x */ - return regBase; -} - -/******************************************************************************* -* MemoryGetPciBaseAddr - Returns the base address of a PCI window. -* DESCRIPTION: -* This function returns the base address of a PCI window. There are 5 -* possible PCI windows (memory 0 - 3 and one for I/O) for each PCI -* interface as defined in gtMemory.h, used by the CPU's address decoding -* mechanism. -* New in MV6436x -* INPUT: -* pciWindow - Selects one of the PCI windows as defined in Memory.h. -* OUTPUT: -* None. -* RETURN: -* 32 bit PCI window base address. -*******************************************************************************/ -unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow) -{ - unsigned int baseAddrReg, base; - - switch (pciWindow) { - case PCI_0_IO: - baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */ - break; - case PCI_0_MEM0: - baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */ - break; - case PCI_0_MEM1: - baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */ - break; - case PCI_0_MEM2: - baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */ - break; - case PCI_0_MEM3: - baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */ - break; -#ifdef INCLUDE_PCI_1 - case PCI_1_IO: - baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */ - break; - case PCI_1_MEM0: - baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */ - break; - case PCI_1_MEM1: - baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */ - break; - case PCI_1_MEM2: - baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */ - break; - case PCI_1_MEM3: - baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */ - break; -#endif /* INCLUDE_PCI_1 */ - default: - return 0xffffffff; - } - GT_REG_READ (baseAddrReg, &base); - return (base << 16); -} - -/******************************************************************************* -* memoryGetBankSize - Returns the size of a memory bank. -* DESCRIPTION: -* This function returns the size of memory bank as described in -* 'gtMemoryGetBankBaseAddress' function. -* INPUT: -* bank - Selects one of the four banks as defined in Memory.h. -* OUTPUT: -* None. -* RETURN: -* 32 bit size memory bank size or 0 for a closed or non populated bank. -* -*******************************************************************************/ -unsigned int memoryGetBankSize (MEMORY_BANK bank) -{ - unsigned int sizeReg, size; - MEMORY_WINDOW window; - - switch (bank) { - case BANK0: - sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /* CS_0_SIZE; */ - window = CS_0_WINDOW; - break; - case BANK1: - sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /* CS_1_SIZE; */ - window = CS_1_WINDOW; - break; - case BANK2: - sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /* CS_2_SIZE; */ - window = CS_2_WINDOW; - break; - case BANK3: - sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /* CS_3_SIZE; */ - window = CS_3_WINDOW; - break; - default: - return 0; - break; - } - /* If the window is closed, a size of 0 is returned */ - if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED) - return 0; - GT_REG_READ (sizeReg, &size); - size = ((size << 16) | 0xffff) + 1; - return size; -} - -/******************************************************************************* -* memoryGetDeviceSize - Returns the size of a device memory space. -* DESCRIPTION: -* This function returns the memory space size of a given device. -* INPUT: -* device - Selects one of the five devices as defined in Memory.h. -* OUTPUT: -* None. -* RETURN: -* 32 bit size of a device memory space. -*******************************************************************************/ -unsigned int memoryGetDeviceSize (DEVICE device) -{ - unsigned int sizeReg, size; - MEMORY_WINDOW window; - - switch (device) { - case DEVICE0: - sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */ - window = DEVCS_0_WINDOW; - break; - case DEVICE1: - sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */ - window = DEVCS_1_WINDOW; - break; - case DEVICE2: - sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */ - window = DEVCS_2_WINDOW; - break; - case DEVICE3: - sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */ - window = DEVCS_3_WINDOW; - break; - case BOOT_DEVICE: - sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */ - window = BOOT_CS_WINDOW; - break; - default: - return 0; - break; - } - /* If the window is closed, a size of 0 is returned */ - if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED) - return 0; - GT_REG_READ (sizeReg, &size); - size = ((size << 16) | 0xffff) + 1; - return size; -} - -/******************************************************************************* -* MemoryGetPciWindowSize - Returns the size of a PCI memory window. -* DESCRIPTION: -* This function returns the size of a PCI window. -* INPUT: -* pciWindow - Selects one of the PCI memory windows as defined in -* Memory.h. -* OUTPUT: -* None. -* RETURN: -* 32 bit size of a PCI memory window. -*******************************************************************************/ -unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow) -{ - unsigned int sizeReg, size; - - switch (pciWindow) { - case PCI_0_IO: - sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */ - break; - case PCI_0_MEM0: - sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */ - break; - case PCI_0_MEM1: - sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */ - break; - case PCI_0_MEM2: - sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */ - break; - case PCI_0_MEM3: - sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */ - break; -#ifdef INCLUDE_PCI_1 - case PCI_1_IO: - sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */ - break; - case PCI_1_MEM0: - sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */ - break; - case PCI_1_MEM1: - sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */ - break; - case PCI_1_MEM2: - sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */ - break; - case PCI_1_MEM3: - sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */ - break; -#endif /* INCLUDE_PCI_1 */ - default: - return 0x0; - } - /* If the memory window is disabled, retrun size = 0 */ - if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow) - == MEM_WINDOW_DISABLED) - return 0; - GT_REG_READ (sizeReg, &size); - size = ((size << 16) | 0xffff) + 1; - return size; -} - -/******************************************************************************* -* memoryGetDeviceWidth - Returns the width of a given device. -* DESCRIPTION: -* The MV's device interface supports up to 32 Bit wide devices. A device -* can have a 1, 2, 4 or 8 Bytes data width. This function returns the -* width of a device as defined by the user or the operating system. -* INPUT: -* device - Selects one of the five devices as defined in Memory.h. -* OUTPUT: -* None. -* RETURN: -* Device width in Bytes (1,2,4 or 8), 0 if error had occurred. -*******************************************************************************/ -unsigned int memoryGetDeviceWidth (DEVICE device) -{ - unsigned int width; - unsigned int regValue; - - GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, ®Value); - width = (regValue & (BIT20 | BIT21)) >> 20; - return (BIT0 << width); -} - -/******************************************************************************* -* memoryMapBank - Set new base address and size for one of the memory -* banks. -* -* DESCRIPTION: -* The CPU interface address decoding map consists of 21 address windows -* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each -* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte -* space. Each address window is defined by two registers - base and size. -* The CPU address is compared with the values in the various CPU windows -* until a match is found and the address is than targeted to that window. -* This function sets new base and size for one the memory banks -* (CS0 - CS3). It is the programmer`s responsibility to make sure that -* there are no conflicts with other memory spaces. When two memory spaces -* overlap, the MV's behavior is not defined .If a bank needs to be closed, -* set the 'bankLength' parameter size to 0x0. -* -* INPUT: -* bank - One of the memory banks (CS0-CS3) as defined in gtMemory.h. -* bankBase - The memory bank base address. -* bankLength - The memory bank size. This function will decrement the -* 'bankLength' parameter by one and then check if the size is -* valid. A valid size must be programed from LSB to MSB as -* sequence of '1's followed by sequence of '0's. -* To close a memory window simply set the size to 0. -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* OUTPUT: -* None. -* RETURN: -* false for invalid size, true otherwise. -* -* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!! -* -*******************************************************************************/ - -bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase, - unsigned int bankLength) -{ - unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift; - -/* PCI_INTERNAL_BAR pciBAR; */ - - switch (bank) { - case BANK0: - baseReg = SCS_0_LOW_DECODE_ADDRESS; /*CS_0_BASE_ADDR; */ - sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /*CS_0_SIZE; */ -/* pciBAR = PCI_CS0_BAR; */ - break; - case BANK1: - baseReg = SCS_1_LOW_DECODE_ADDRESS; /*CS_1_BASE_ADDR; */ - sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /*CS_1_SIZE; */ - /* pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */ - break; - case BANK2: - baseReg = SCS_2_LOW_DECODE_ADDRESS; /*CS_2_BASE_ADDR; */ - sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /*CS_2_SIZE; */ -/* pciBAR = PCI_CS2_BAR;*/ - break; - case BANK3: - baseReg = SCS_3_LOW_DECODE_ADDRESS; /*CS_3_BASE_ADDR; */ - sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /*CS_3_SIZE; */ -/* pciBAR = PCI_CS3_BAR; */ - break; - default: - return false; - } - /* If the size is 0, the window will be disabled */ - if (bankLength == 0) { - MemoryDisableWindow (CS_0_WINDOW << bank); - /* Disable the BAR from the PCI slave side */ -/* gtPci0DisableInternalBAR(pciBAR); */ -/* gtPci1DisableInternalBAR(pciBAR); */ - return true; - } - /* The base address must be aligned to the size */ - if ((bankBase % bankLength) != 0) { - return false; - } - if (bankLength >= MINIMUM_MEM_BANK_SIZE) { - newBase = bankBase >> 16; - newSize = bankLength >> 16; - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - temp = newSize - 1; - for (rShift = 0; rShift < 16; rShift++) { - temp = temp >> rShift; - if ((temp & 0x1) == 0) { /* Either we got to the last '1' */ - /* or the size is not valid */ - if (temp > 0x0) - return false; - else - break; - } - } -#ifdef DEBUG - { - unsigned int oldBase, oldSize; - - GT_REG_READ (baseReg, &oldBase); - GT_REG_READ (sizeReg + 8, &oldSize); - - printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n", - bank, oldBase, oldSize, newBase, newSize); - } -#endif - /* writing the new values */ - GT_REG_WRITE (baseReg, newBase); - GT_REG_WRITE (sizeReg, newSize - 1); - /* Enable back the window */ - MemoryEnableWindow (CS_0_WINDOW << bank); - /* Enable the BAR from the PCI slave side */ -/* gtPci0EnableInternalBAR(pciBAR); */ -/* gtPci1EnableInternalBAR(pciBAR); */ - return true; - } - return false; -} - - -/******************************************************************************* -* memoryMapDeviceSpace - Set new base address and size for one of the device -* windows. -* -* DESCRIPTION: -* The CPU interface address decoding map consists of 21 address windows -* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each -* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte -* space. Each address window is defined by two registers - base and size. -* The CPU address is compared with the values in the various CPU windows -* until a match is found and the address is than targeted to that window. -* This function sets new base and size for one the device windows -* (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure -* that there are no conflicts with other memory spaces. When two memory -* spaces overlap, the MV's behavior is not defined .If a device window -* needs to be closed, set the 'deviceLength' parameter size to 0x0. -* -* INPUT: -* device - One of the device windows (DEV_CS0-DEV_CS3) as -* defined in gtMemory.h. -* deviceBase - The device window base address. -* deviceLength - The device window size. This function will decrement -* the 'deviceLength' parameter by one and then -* check if the size is valid. A valid size must be -* programed from LSB to MSB as sequence of '1's -* followed by sequence of '0's. -* To close a memory window simply set the size to 0. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* -* OUTPUT: -* None. -* -* RETURN: -* false for invalid size, true otherwise. -* -* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!! -* -*******************************************************************************/ - -bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase, - unsigned int deviceLength) -{ - unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift; - -/* PCI_INTERNAL_BAR pciBAR;*/ - - switch (device) { - case DEVICE0: - baseReg = CS_0_LOW_DECODE_ADDRESS; /*DEV_CS0_BASE_ADDR; */ - sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */ -/* pciBAR = PCI_DEV_CS0_BAR; */ - break; - case DEVICE1: - baseReg = CS_1_LOW_DECODE_ADDRESS; /*DEV_CS1_BASE_ADDR; */ - sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */ -/* pciBAR = PCI_DEV_CS1_BAR; */ - break; - case DEVICE2: - baseReg = CS_2_LOW_DECODE_ADDRESS; /*DEV_CS2_BASE_ADDR; */ - sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */ -/* pciBAR = PCI_DEV_CS2_BAR; */ - break; - case DEVICE3: - baseReg = CS_3_LOW_DECODE_ADDRESS; /*DEV_CS3_BASE_ADDR; */ - sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */ -/* pciBAR = PCI_DEV_CS3_BAR; */ - break; - case BOOT_DEVICE: - baseReg = BOOTCS_LOW_DECODE_ADDRESS; /*BOOTCS_BASE_ADDR; */ - sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */ -/* pciBAR = PCI_BOOT_CS_BAR; */ - break; - default: - return false; - } - if (deviceLength == 0) { - MemoryDisableWindow (DEVCS_0_WINDOW << device); - /* Disable the BAR from the PCI slave side */ -/* gtPci0DisableInternalBAR(pciBAR); */ -/* gtPci1DisableInternalBAR(pciBAR); */ - return true; - } - /* The base address must be aligned to the size */ - if ((deviceBase % deviceLength) != 0) { - return false; - } - if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) { - newBase = deviceBase >> 16; - newSize = deviceLength >> 16; - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - temp = newSize - 1; - for (rShift = 0; rShift < 16; rShift++) { - temp = temp >> rShift; - if ((temp & 0x1) == 0) { /* Either we got to the last '1' */ - /* or the size is not valid */ - if (temp > 0x0) - return false; - else - break; - } - } - /* writing the new values */ - GT_REG_WRITE (baseReg, newBase); - GT_REG_WRITE (sizeReg, newSize - 1); - MemoryEnableWindow (DEVCS_0_WINDOW << device); - /* Enable the BAR from the PCI slave side */ -/* gtPci0EnableInternalBAR(pciBAR); */ -/* gtPci1EnableInternalBAR(pciBAR); */ - return true; - } - return false; -} - -/******************************************************************************* -* MemorySetPciWindow - Set new base address and size for one of the PCI -* windows. -* -* DESCRIPTION: -* The CPU interface address decoding map consists of 21 address windows -* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each -* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte -* space. Each address window is defined by two registers - base and size. -* The CPU address is compared with the values in the various CPU windows -* until a match is found and the address is than targeted to that window. -* This function sets new base and size for one the PCI windows -* (PCI memory0/1/2..). It is the programmer`s responsibility to make sure -* that there are no conflicts with other memory spaces. When two memory -* spaces overlap, the MV's behavior is not defined. If a PCI window -* needs to be closed, set the 'pciWindowSize' parameter size to 0x0. -* -* INPUT: -* pciWindow - One of the PCI windows as defined in gtMemory.h. -* pciWindowBase - The PCI window base address. -* pciWindowSize - The PCI window size. This function will decrement the -* 'pciWindowSize' parameter by one and then check if the -* size is valid. A valid size must be programed from LSB -* to MSB as sequence of '1's followed by sequence of '0's. -* To close a memory window simply set the size to 0. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* -* OUTPUT: -* None. -* -* RETURN: -* false for invalid size, true otherwise. -* -*******************************************************************************/ -bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase, - unsigned int pciWindowSize) -{ - unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift; - - switch (pciWindow) { - case PCI_0_IO: - baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */ - sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */ - break; - case PCI_0_MEM0: - baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */ - sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */ - break; - case PCI_0_MEM1: - baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */ - sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */ - break; - case PCI_0_MEM2: - baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */ - sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */ - break; - case PCI_0_MEM3: - baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */ - sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */ - break; -#ifdef INCLUDE_PCI_1 - case PCI_1_IO: - baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */ - sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */ - break; - case PCI_1_MEM0: - baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */ - sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */ - break; - case PCI_1_MEM1: - baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */ - sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */ - break; - case PCI_1_MEM2: - baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */ - sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */ - break; - case PCI_1_MEM3: - baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */ - sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */ - break; -#endif /* INCLUDE_PCI_1 */ - default: - return false; - } - if (pciWindowSize == 0) { - MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow); - return true; - } - /* The base address must be aligned to the size */ - if ((pciWindowBase % pciWindowSize) != 0) { - return false; - } - if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) { - pciWindowBase >>= 16; - pciWindowSize >>= 16; - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - temp = pciWindowSize - 1; - for (rShift = 0; rShift < 16; rShift++) { - temp = temp >> rShift; - if ((temp & 0x1) == 0) { /* Either we got to the last '1' */ - /* or the size is not valid */ - if (temp > 0x0) - return false; - else - break; - } - } - GT_REG_WRITE (sizeReg, pciWindowSize - 1); - GT_REG_READ (baseAddrReg, ¤tLow); - pciWindowBase = - (pciWindowBase & 0xfffff) | (currentLow & 0xfff00000); - GT_REG_WRITE (baseAddrReg, pciWindowBase); - MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow); - return true; - } - return false; -} - -/******************************************************************************* -* memoryMapInternalRegistersSpace - Sets new base address for the internal -* registers memory space. -* -* DESCRIPTION: -* This function set new base address for the internal registers memory -* space (the size is fixed and cannot be modified). The function does not -* handle overlapping with other memory spaces, it is the programer's -* responsibility to ensure that overlapping does not occur. -* When two memory spaces overlap, the MV's behavior is not defined. -* -* INPUT: -* internalRegBase - new base address for the internal registers memory -* space. -* -* OUTPUT: -* None. -* -* RETURN: -* true on success, false on failure -* -*******************************************************************************/ -/******************************************************************** -* memoryMapInternalRegistersSpace - Sets new base address for the internals -* registers. -* -* INPUTS: unsigned int internalRegBase - The new base address. -* RETURNS: true on success, false on failure -*********************************************************************/ -bool memoryMapInternalRegistersSpace (unsigned int internalRegBase) -{ - unsigned int currentValue; - unsigned int internalValue = internalRegBase; - - internalRegBase = (internalRegBase >> 16); - GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue); - internalRegBase = (currentValue & 0xff000000) | internalRegBase; - GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase); - /* initializing also the global variable 'internalRegBaseAddr' */ -/* gtInternalRegBaseAddr = internalValue; */ - INTERNAL_REG_BASE_ADDR = internalValue; - return true; -} - -/******************************************************************************* -* memoryGetInternalRegistersSpace - Returns the internal registers Base -* address. -* -* DESCRIPTION: -* This function returns the base address of the internal registers -* memory space . -* -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* 32 bit base address of the internal registers memory space. -* -*******************************************************************************/ -unsigned int memoryGetInternalRegistersSpace (void) -{ - unsigned int currentValue = 0; - - GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue); - return ((currentValue & 0x000fffff) << 16); -} - -/******************************************************************************* -* gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address. -* -* DESCRIPTION: -* The Atlantis incorporate integrated 2Mbit SRAM for general use. This -* funcnion return the SRAM's base address. -* INPUT: -* None. -* OUTPUT: -* None. -* RETURN: -* 32 bit SRAM's base address. -* -*******************************************************************************/ -unsigned int memoryGetInternalSramBaseAddr (void) -{ - return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16); -} - -/******************************************************************************* -* gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address. -* -* DESCRIPTION: -* The Atlantis incorporate integrated 2Mbit SRAM for general use. This -* function sets a new base address to the SRAM . -* INPUT: -* sramBaseAddress - The SRAM's base address. -* OUTPUT: -* None. -* RETURN: -* None. -* -*******************************************************************************/ -void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress) -{ - GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16); -} - -/******************************************************************************* -* memorySetProtectRegion - Set protection mode for one of the 8 regions. -* -* DESCRIPTION: -* The CPU interface supports configurable access protection. This includes -* up to eight address ranges defined to a different protection type : -* whether the address range is cacheable or not, whether it is writable or -* not , and whether it is accessible or not. A Low and High registers -* define each window while the minimum address range of each window is -* 1Mbyte. An address driven by the CPU, in addition to the address -* decoding and remapping process, is compared against the eight Access -* Protection Low/High registers , if an address matches one of the windows -* , the MV device checks the transaction type against the protection bits -* defined in CPU Access Protection register, to determine if the access is -* allowed. This function set a protection mode to one of the 8 possible -* regions. -* NOTE: -* The CPU address windows are restricted to a size of 2 power n and the -* start address must be aligned to the window size. For example, if using -* a 16 MB window, the start address bits [23:0] must be 0.The MV's -* internal registers space is not protected, even if the access protection -* windows contain this space. -* -* INPUT: -* region - selects which region to be configured. The values defined in -* gtMemory.h: -* -* - MEM_REGION0 -* - MEM_REGION1 -* - etc. -* -* memAccess - Allows or forbids access (read or write ) to the region. The -* values defined in gtMemory.h: -* -* - MEM_ACCESS_ALLOWED -* - MEM_ACCESS_FORBIDEN -* -* memWrite - CPU write protection to the region. The values defined in -* gtMemory.h: -* -* - MEM_WRITE_ALLOWED -* - MEM_WRITE_FORBIDEN -* -* cacheProtection - Defines whether caching the region is allowed or not. -* The values defined in gtMemory.h: -* -* - MEM_CACHE_ALLOWED -* - MEM_CACHE_FORBIDEN -* -* baseAddress - the region's base Address. -* regionSize - The region's size. This function will decrement the -* 'regionSize' parameter by one and then check if the size -* is valid. A valid size must be programed from LSB to MSB -* as sequence of '1's followed by sequence of '0's. -* To close a memory window simply set the size to 0. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* -* OUTPUT: -* None. -* -* RETURN: -* false for invalid size, true otherwise. -* -*******************************************************************************/ -bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window, - MEMORY_ACCESS memAccess, - MEMORY_ACCESS_WRITE memWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, unsigned int size) -{ - unsigned int dataForReg, temp, rShift; - - if (size == 0) { - GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window), - 0x0); - return true; - } - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size >= MINIMUM_ACCESS_WIN_SIZE) { - baseAddress = ((baseAddress >> 16) & 0xfffff); - dataForReg = baseAddress | ((memAccess << 20) & BIT20) | - ((memWrite << 21) & BIT21) | ((cacheProtection << 22) - & BIT22) | BIT31; - GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window, - dataForReg); - size >>= 16; - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - temp = size - 1; - for (rShift = 0; rShift < 16; rShift++) { - temp = temp >> rShift; - if ((temp & 0x1) == 0) { /* Either we got to the last '1' */ - /* or the size is not valid */ - if (temp > 0x0) - return false; - else - break; - } - } - GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window), - size - 1); - return true; - } - return false; -} - -/******************************************************************************* -* gtMemoryDisableProtectRegion - Disable a protected window. -* -* DESCRIPTION: -* This function disable a protected window set by -* 'gtMemorySetProtectRegion' function. -* -* INPUT: -* window - one of the 4 windows ( defined in gtMemory.h ). -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ -void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window) -{ - RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)), - BIT31); -} - -/******************************************************************************* -* memorySetPciRemapValue - Set a remap value to a PCI memory space target. -* -* DESCRIPTION: -* In addition to the address decoding mechanism, the CPU has an address -* remapping mechanism to be used by every PCI decoding window. Each PCI -* window can be remaped to a desired address target according to the remap -* value within the remap register. The address remapping is useful when a -* CPU address range must be reallocated to a different location on the -* PCI bus. Also, it enables CPU access to a PCI agent located above the -* 4Gbyte space. On system boot, each of the PCI memory spaces is maped to -* a defualt value (see CPU interface section in the MV spec for the -* default values). The remap mechanism does not always produce the desired -* address on the PCI bus because of the remap mechanism way of working -* (to fully understand why, please see the 'Address Remapping' section in -* the MV's spec). Therefor, this function sets a desired remap value to -* one of the PCI memory windows and return the effective address that -* should be used when exiting the PCI memory window. You should ALWAYS use -* the returned value by this function when remapping a PCI window and -* exiting it. If for example the base address of PCI0 memory 0 is -* 0x90000000, the size is 0x03ffffff and the remap value is 0x11000000, -* the function will return the value of 0x91000000 that MUST -* be used to exit this memory window in order to achive the deisred -* remapping. -* -* INPUT: -* memoryWindow - One of the PCI memory windows as defined in Memory.h -* remapValueLow - The low remap value. -* remapValueHigh - The high remap value. -* OUTPUT: -* None. -* -* RETURN: -* The effective base address to exit the PCI, or 0xffffffff if one of the -* parameters is erroneous or the effective base address is higher the top -* decode value. -* -*******************************************************************************/ -unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow, - unsigned int remapValueHigh, - unsigned int remapValueLow) -{ - unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0; - unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0; - unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh; - - /* Initializing the base and size variables of the PCI - memory windows */ - switch (memoryWindow) { - case PCI_0_IO: - pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR; - pciMemWindowSizeReg = PCI_0_IO_SIZE; - remapRegLow = PCI_0_IO_ADDR_REMAP; - remapRegHigh = PCI_0_IO_ADDR_REMAP; - break; - case PCI_0_MEM0: - pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR; - pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE; - remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP; - remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP; - break; - case PCI_0_MEM1: - pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR; - pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE; - remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP; - remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP; - break; - case PCI_0_MEM2: - pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR; - pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE; - remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP; - remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP; - break; - case PCI_0_MEM3: - pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR; - pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE; - remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP; - remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP; - break; -#ifdef INCLUDE_PCI_1 - case PCI_1_IO: - pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR; - pciMemWindowSizeReg = PCI_1_IO_SIZE; - remapRegLow = PCI_1_IO_ADDR_REMAP; - remapRegHigh = PCI_1_IO_ADDR_REMAP; - break; - case PCI_1_MEM0: - pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR; - pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE; - remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP; - remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP; - break; - case PCI_1_MEM1: - pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR; - pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE; - remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP; - remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP; - break; - case PCI_1_MEM2: - pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR; - pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE; - remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP; - remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP; - break; - case PCI_1_MEM3: - pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR; - pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE; - remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP; - remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP; - break; -#endif /* INCLUDE_PCI_1 */ - default: - /* Retrun an invalid effective base address */ - return 0xffffffff; - } - /* Writing the remap value to the remap regisers */ - GT_REG_WRITE (remapRegHigh, remapValueHigh); - GT_REG_WRITE (remapRegLow, remapValueLow >> 16); - /* Reading the values from the base address and size registers */ - baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff; - windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff; - /* Start calculating the effective Base Address */ - effectiveBaseAddress = baseAddrValue << 16; - /* The effective base address will be combined from the chopped (if any) - remap value (according to the size value and remap mechanism) and the - window's base address */ - effectiveBaseAddress |= - (((windowSizeValue << 16) | 0xffff) & remapValueLow); - /* If the effectiveBaseAddress exceed the window boundaries return an - invalid value. */ - if (effectiveBaseAddress > - ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff))) - return 0xffffffff; - return effectiveBaseAddress; -} - -/******************************************************************** -* memorySetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency. -* -* -* Inputs: SNOOP_REGION region - One of the four regions. -* SNOOP_TYPE snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* unsigned int baseAddress - Base Address of this region. -* unsigned int topAddress - Top Address of this region. -* Returns: false if one of the parameters is wrong and true else -*********************************************************************/ -/* evb6260 code */ -#if 0 -bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, - MEMORY_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) ) - return false; - snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region; - snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region; - if(regionLength == 0) /* closing the region */ - { - GT_REG_WRITE(snoopXbaseAddress,0x0000ffff); - GT_REG_WRITE(snoopXtopAddress,0); - return true; - } - baseAddress = baseAddress & 0xffff0000; - data = (baseAddress >> 16) | snoopType << 16; - GT_REG_WRITE(snoopXbaseAddress,data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1); - return true; -} -#endif - -/******************************************************************** -* memoryRemapAddress - This fubction used for address remapping. -* -* -* Inputs: regOffset: remap register -* remapValue : -* Returns: false if one of the parameters is erroneous,true otherwise. -* -* Not needed function To_do !!!! -*********************************************************************/ -bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue) -{ - unsigned int valueForReg; - - valueForReg = (remapValue & 0xfff00000) >> 20; - GT_REG_WRITE (remapReg, valueForReg); - return true; -} - -/******************************************************************************* -* memoryGetDeviceParam - Extract the device parameters from the device bank -* parameters register. -* -* DESCRIPTION: -* To allow interfacing with very slow devices and fast synchronous SRAMs, -* each device can be programed to different timing parameters. Each bank -* has its own parameters register. Bank width can be programmed to 8, 16, -* or 32-bits. Bank timing parameters can be programmed to support -* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O -* Controllers). The MV allows you to set timing parameters and width for -* each device through parameters register . -* This function extracts the parameters described from the Device Bank -* parameters register and fills the given 'deviceParam' (defined in -* gtMemory.h) structure with the read data. -* -* INPUT: -* deviceParam - pointer to a structure DEVICE_PARAM (defined in -* Memory.h).For details about each structure field please -* see the device timing parameter section in the MV -* datasheet. -* deviceNum - Select on of the five device banks (defined in -* Memory.h) : -* -* - DEVICE0 -* - DEVICE1 -* - DEVICE2 -* - etc. -* -* OUTPUT: -* None. -* -* RETURN: -* false if one of the parameters is erroneous,true otherwise. -* -*******************************************************************************/ -/******************************************************************** -* memoryGetDeviceParam - This function used for getting device parameters from -* DEVICE BANK PARAMETERS REGISTER -* -* -* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK -* PARAMETERS REGISTER -* - deviceNum : number of device -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ - -bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum) -{ - unsigned int valueOfReg; - unsigned int calcData; - - if (deviceNum > 4) - return false; - GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg); - calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19); - deviceParam->turnOff = calcData; /* Turn Off */ - - calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19); - deviceParam->acc2First = calcData; /* Access To First */ - - calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20); - deviceParam->acc2Next = calcData; /* Access To Next */ - - calcData = - ((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22); - deviceParam->ale2Wr = calcData; /* Ale To Write */ - - calcData = ((0x1c000 & valueOfReg) >> 14) + - ((BIT26 & valueOfReg) >> 23); - deviceParam->wrLow = calcData; /* Write Active */ - - calcData = ((0xe0000 & valueOfReg) >> 17) + - ((BIT27 & valueOfReg) >> 24); - deviceParam->wrHigh = calcData; /* Write High */ - - calcData = ((0x300000 & valueOfReg) >> 20); - deviceParam->deviceWidth = (BIT0 << calcData); /* In bytes */ - calcData = ((0x30000000 & valueOfReg) >> 28); - deviceParam->badrSkew = calcData; /* Cycles gap between BAdr - toggle to read data sample. */ - calcData = ((0x40000000 & valueOfReg) >> 30); - deviceParam->DPEn = calcData; /* Data Parity enable */ - return true; -} - -/******************************************************************************* -* memorySetDeviceParam - Set new parameters for a device. -* -* -* DESCRIPTION: -* To allow interfacing with very slow devices and fast synchronous SRAMs, -* each device can be programed to different timing parameters. Each bank -* has its own parameters register. Bank width can be programmed to 8, 16, -* or 32-bits. Bank timing parameters can be programmed to support -* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O -* Controllers). The MV allows you to set timing parameters and width for -* each device through parameters register. This function set new -* parameters to a device Bank from the delivered structure 'deviceParam' -* (defined in gtMemory.h). The structure must be initialized with data -* prior to the use of these function. -* -* INPUT: -* deviceParam - pointer to a structure DEVICE_PARAM (defined in -* Memory.h).For details about each structure field please -* see the device timing parameter section in the MV -* datasheet. -* deviceNum - Select on of the five device banks (defined in -* Memory.h) : -* -* - DEVICE0 -* - DEVICE1 -* - DEVICE2 -* - etc. -* -* OUTPUT: -* None. -* -* RETURN: -* false if one of the parameters is erroneous,true otherwise. -* -*******************************************************************************/ -/******************************************************************** -* memorySetDeviceParam - This function used for setting device parameters to -* DEVICE BANK PARAMETERS REGISTER -* -* -* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK -* PARAMETERS REGISTER -* - deviceNum : number of device -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ -bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum) -{ - unsigned int valueForReg; - - if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) || - (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) || - (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) || - (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) { - return false; - } - valueForReg = (((deviceParam->turnOff) & 0x7) | - (((deviceParam->turnOff) & 0x8) << 19) | - (((deviceParam->acc2First) & 0xf) << 3) | - (((deviceParam->acc2First) & 0x10) << 19) | - (((deviceParam->acc2Next) & 0xf) << 7) | - (((deviceParam->acc2Next) & 0x10) << 20) | - (((deviceParam->ale2Wr) & 0x7) << 11) | - (((deviceParam->ale2Wr) & 0xf) << 22) | - (((deviceParam->wrLow) & 0x7) << 14) | - (((deviceParam->wrLow) & 0xf) << 23) | - (((deviceParam->wrHigh) & 0x7) << 17) | - (((deviceParam->wrHigh) & 0xf) << 24) | - (((deviceParam->badrSkew) & 0x3) << 28) | - (((deviceParam->DPEn) & 0x1) << 30)); - - /* insert the device width: */ - switch (deviceParam->deviceWidth) { - case 1: - valueForReg = valueForReg | _8BIT; - break; - case 2: - valueForReg = valueForReg | _16BIT; - break; - case 4: - valueForReg = valueForReg | _32BIT; - break; - default: - valueForReg = valueForReg | _8BIT; - break; - } - GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg); - return true; -} - -/******************************************************************************* -* MemoryDisableWindow - Disable a memory space by the disable bit. -* DESCRIPTION: -* This function disables one of the 21 availiable windows dedicated for -* the CPU decoding mechanism. Its possible to combine several windows with -* the OR command. -* INPUT: -* window - One or more of the memory windows (defined in gtMemory.h). -* OUTPUT: -* None. -* RETURN: -* None. -*******************************************************************************/ -void MemoryDisableWindow (MEMORY_WINDOW window) -{ - SET_REG_BITS (BASE_ADDR_ENABLE, window); -} - -/******************************************************************************* -* MemoryEnableWindow - Enable a memory space that was disabled by -* 'MemoryDisableWindow'. -* DESCRIPTION: -* This function enables one of the 21 availiable windows dedicated for the -* CPU decoding mechanism. Its possible to combine several windows with the -* OR command. -* INPUT: -* window - One or more of the memory windows (defined in gtMemory.h). -* OUTPUT: -* None. -* RETURN: -* None. -*******************************************************************************/ -void MemoryEnableWindow (MEMORY_WINDOW window) -{ - RESET_REG_BITS (BASE_ADDR_ENABLE, window); -} - -/******************************************************************************* -* MemoryGetMemWindowStatus - This function check whether the memory window is -* disabled or not. -* DESCRIPTION: -* This function checks if the given memory window is closed . -* INPUT: -* window - One or more of the memory windows (defined in gtMemory.h). -* OUTPUT: -* None. -* RETURN: -* true for a closed window, false otherwise . -*******************************************************************************/ -MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window) -{ - if (GTREGREAD (BASE_ADDR_ENABLE) & window) - return MEM_WINDOW_DISABLED; - return MEM_WINDOW_ENABLED; -} diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c deleted file mode 100644 index 7839b68..0000000 --- a/board/Marvell/common/ns16550.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * COM1 NS16550 support - * originally from linux source (arch/powerpc/boot/ns16550.c) - * modified to use CONFIG_SYS_ISA_MEM and new defines - * - * further modified by Josh Huber <huber@mclx.com> to support - * the DUART on the Galileo Eval board. (db64360) - */ - -#include <config.h> -#include "ns16550.h" - -#ifdef ZUMA_NTL -/* no 16550 device */ -#else -const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0), - (NS16550_t) (CONFIG_SYS_DUART_IO + 0x20) -}; - -volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) -{ - volatile struct NS16550 *com_port; - - com_port = (struct NS16550 *) COM_PORTS[chan]; - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ - - /* Clear & enable FIFOs */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; - return (com_port); -} - -void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor) -{ - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ - - /* Clear & enable FIFOs */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; -} - -void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c) -{ - while ((com_port->lsr & LSR_THRE) == 0); - com_port->thr = c; -} - -unsigned char NS16550_getc (volatile struct NS16550 *com_port) -{ - while ((com_port->lsr & LSR_DR) == 0); - return (com_port->rbr); -} - -int NS16550_tstc (volatile struct NS16550 *com_port) -{ - return ((com_port->lsr & LSR_DR) != 0); -} -#endif diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h deleted file mode 100644 index 9306381..0000000 --- a/board/Marvell/common/ns16550.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * NS16550 Serial Port - * originally from linux source (arch/powerpc/boot/ns16550.h) - * modified slightly to - * have addresses as offsets from CONFIG_SYS_ISA_BASE - * added a few more definitions - * added prototypes for ns16550.c - * reduced no of com ports to 2 - * modifications (c) Rob Taylor, Flying Pig Systems. 2000. - * - * further modified to support the DUART in the Galileo eval board - * modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - */ - -#ifndef __NS16550_H__ -#define __NS16550_H__ - -/* the padding is necessary because on the galileo board the UART is - wired in with the 3 address lines shifted over by 2 bits */ -struct NS16550 -{ - unsigned char rbr; /* 0 = 0-3*/ - int pad1:24; - - unsigned char ier; /* 1 = 4-7*/ - int pad2:24; - - unsigned char fcr; /* 2 = 8-b*/ - int pad3:24; - - unsigned char lcr; /* 3 = c-f*/ - int pad4:24; - - unsigned char mcr; /* 4 = 10-13*/ - int pad5:24; - - unsigned char lsr; /* 5 = 14-17*/ - int pad6:24; - - unsigned char msr; /* 6 =18-1b*/ - int pad7:24; - - unsigned char scr; /* 7 =1c-1f*/ - int pad8:24; -} __attribute__ ((packed)); - -/* aliases */ -#define thr rbr -#define iir fcr -#define dll rbr -#define dlm ier - -#define FCR_FIFO_EN 0x01 /*fifo enable*/ -#define FCR_RXSR 0x02 /*receiver soft reset*/ -#define FCR_TXSR 0x04 /*transmitter soft reset*/ - - -#define MCR_DTR 0x01 -#define MCR_RTS 0x02 -#define MCR_DMA_EN 0x04 -#define MCR_TX_DFR 0x08 - - -#define LCR_WLS_MSK 0x03 /* character length slect mask*/ -#define LCR_WLS_5 0x00 /* 5 bit character length */ -#define LCR_WLS_6 0x01 /* 6 bit character length */ -#define LCR_WLS_7 0x02 /* 7 bit character length */ -#define LCR_WLS_8 0x03 /* 8 bit character length */ -#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define LCR_PEN 0x08 /* Parity eneble*/ -#define LCR_EPS 0x10 /* Even Parity Select*/ -#define LCR_STKP 0x20 /* Stick Parity*/ -#define LCR_SBRK 0x40 /* Set Break*/ -#define LCR_BKSE 0x80 /* Bank select enable*/ - -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -/* useful defaults for LCR*/ -#define LCR_8N1 0x03 - - -#define COM1 0x03F8 -#define COM2 0x02F8 - -volatile struct NS16550 * NS16550_init(int chan, int baud_divisor); -void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c); -unsigned char NS16550_getc(volatile struct NS16550 *com_port); -int NS16550_tstc(volatile struct NS16550 *com_port); -void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor); - -typedef struct NS16550 *NS16550_t; - -extern const NS16550_t COM_PORTS[]; - -#endif diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c deleted file mode 100644 index 432aa06..0000000 --- a/board/Marvell/common/serial.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus <ingo.assmus@keymile.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * serial.c - serial support for the gal ev board - */ - -/* supports both the 16650 duart and the MPSC */ - -#include <common.h> -#include <command.h> -#include <serial.h> -#include <linux/compiler.h> - -#include "../include/memory.h" - -#include "ns16550.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_MPSC -static int marvell_serial_init(void) -{ -#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) - int clock_divisor = 230400 / gd->baudrate; -#endif - - mpsc_init (gd->baudrate); - - /* init the DUART chans so that KGDB in the kernel can use them */ -#ifdef CONFIG_SYS_INIT_CHAN1 - NS16550_reinit (COM_PORTS[0], clock_divisor); -#endif -#ifdef CONFIG_SYS_INIT_CHAN2 - NS16550_reinit (COM_PORTS[1], clock_divisor); -#endif - return (0); -} - -static void marvell_serial_putc(const char c) -{ - if (c == '\n') - mpsc_putchar ('\r'); - - mpsc_putchar (c); -} - -static int marvell_serial_getc(void) -{ - return mpsc_getchar (); -} - -static int marvell_serial_tstc(void) -{ - return mpsc_test_char (); -} - -static void marvell_serial_setbrg(void) -{ - galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); -} - -#else /* ! CONFIG_MPSC */ - -static int marvell_serial_init(void) -{ - int clock_divisor = 230400 / gd->baudrate; - -#ifdef CONFIG_SYS_INIT_CHAN1 - (void) NS16550_init (0, clock_divisor); -#endif -#ifdef CONFIG_SYS_INIT_CHAN2 - (void) NS16550_init (1, clock_divisor); -#endif - return (0); -} - -static void marvell_serial_putc(const char c) -{ - if (c == '\n') - NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); - - NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c); -} - -static int marvell_serial_getc(void) -{ - return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); -} - -static int marvell_serial_tstc(void) -{ - return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); -} - -static void marvell_serial_setbrg(void) -{ - int clock_divisor = 230400 / gd->baudrate; - -#ifdef CONFIG_SYS_INIT_CHAN1 - NS16550_reinit (COM_PORTS[0], clock_divisor); -#endif -#ifdef CONFIG_SYS_INIT_CHAN2 - NS16550_reinit (COM_PORTS[1], clock_divisor); -#endif -} - -#endif /* CONFIG_MPSC */ - -static struct serial_device marvell_serial_drv = { - .name = "marvell_serial", - .start = marvell_serial_init, - .stop = NULL, - .setbrg = marvell_serial_setbrg, - .putc = marvell_serial_putc, - .puts = default_serial_puts, - .getc = marvell_serial_getc, - .tstc = marvell_serial_tstc, -}; - -void marvell_serial_initialize(void) -{ - serial_register(&marvell_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &marvell_serial_drv; -} - -#if defined(CONFIG_CMD_KGDB) -void kgdb_serial_init (void) -{ -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif diff --git a/board/Marvell/include/memory.h b/board/Marvell/include/memory.h deleted file mode 100644 index 0947b6e..0000000 --- a/board/Marvell/include/memory.h +++ /dev/null @@ -1,173 +0,0 @@ -/* Memory.h - Memory mappings and remapping functions declarations */ - -/* Copyright - Galileo technology. */ - -#ifndef __INCmemoryh -#define __INCmemoryh - -/* includes */ - -#include "core.h" - -/* defines */ - -#define DONT_MODIFY 0xffffffff -#define PARITY_SUPPORT 0x40000000 -#define MINIMUM_MEM_BANK_SIZE 0x10000 -#define MINIMUM_DEVICE_WINDOW_SIZE 0x10000 -#define MINIMUM_PCI_WINDOW_SIZE 0x10000 -#define MINIMUM_ACCESS_WIN_SIZE 0x10000 - -#define _8BIT 0x00000000 -#define _16BIT 0x00100000 -#define _32BIT 0x00200000 -#define _64BIT 0x00300000 - -/* typedefs */ - - typedef struct deviceParam -{ /* boundary values */ - unsigned int turnOff; /* 0x0 - 0xf */ - unsigned int acc2First; /* 0x0 - 0x1f */ - unsigned int acc2Next; /* 0x0 - 0x1f */ - unsigned int ale2Wr; /* 0x0 - 0xf */ - unsigned int wrLow; /* 0x0 - 0xf */ - unsigned int wrHigh; /* 0x0 - 0xf */ - unsigned int badrSkew; /* 0x0 - 0x2 */ - unsigned int DPEn; /* 0x0 - 0x1 */ - unsigned int deviceWidth; /* in Bytes */ -} DEVICE_PARAM; - - -typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK; -typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE; - -/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \ - MEM_REGION3,MEM_REGION4,MEM_REGION5, \ - MEM_REGION6,MEM_REGION7} \ - MEMORY_PROTECT_REGION;*/ -/* There are four possible windows that can be defined as protected */ -typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2, - MEM_WINDOW3 - } MEMORY_PROTECT_WINDOW; -/* When defining a protected window , this paramter indicates whether it - is accessible or not */ -typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \ - MEMORY_ACCESS; -typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \ - MEMORY_ACCESS_WRITE; -typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \ - MEMORY_CACHE_PROTECT; -typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \ - MEMORY_SNOOP_TYPE; -typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \ - MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \ - MEMORY_SNOOP_REGION; - -/* There are 21 memory windows dedicated for the varios interfaces (PCI, - devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's - address decoding mechanism. */ -typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1, - CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3, - DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5, - DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7, - BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9, - PCI_0_MEM0_WINDOW = BIT10, - PCI_0_MEM1_WINDOW = BIT11, - PCI_0_MEM2_WINDOW = BIT12, - PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14, - PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16, - PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18, - INTEGRATED_SRAM_WINDOW = BIT19, - INTERNAL_SPACE_WINDOW = BIT20, - ALL_WINDOWS = 0X1FFFFF - } MEMORY_WINDOW; - -typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED - } MEMORY_WINDOW_STATUS; - - -typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3 -#ifdef INCLUDE_PCI_1 - ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3 -#endif /* INCLUDE_PCI_1 */ - } PCI_MEM_WINDOW; - - -/* -------------------------------------------------------------------------------------------------*/ - -/* functions */ -unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank); -unsigned int memoryGetDeviceBaseAddress(DEVICE device); -/* New at MV6436x */ -unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow); -unsigned int memoryGetBankSize(MEMORY_BANK bank); -unsigned int memoryGetDeviceSize(DEVICE device); -unsigned int memoryGetDeviceWidth(DEVICE device); -/* New at MV6436x */ -unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow); - -/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/ -bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength); -/* Set a new base and size for one of the memory banks (CS0 - CS3) */ -bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase, - unsigned int bankSize); -bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength); - -/* Change the Internal Register Base Address to a new given Address. */ -bool memoryMapInternalRegistersSpace(unsigned int internalRegBase); -/* returns internal Register Space Base Address. */ -unsigned int memoryGetInternalRegistersSpace(void); - -/* Returns the integrated SRAM Base Address. */ -unsigned int memoryGetInternalSramBaseAddr(void); -/* -------------------------------------------------------------------------------------------------*/ - -/* Set new base address for the integrated SRAM. */ -void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress); -/* -------------------------------------------------------------------------------------------------*/ - -/* Delete a protection feature to a given space. */ -void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window); -/* -------------------------------------------------------------------------------------------------*/ - -/* Writes a new remap value to the remap register */ -unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow, - unsigned int remapValueHigh, - unsigned int remapValueLow); -/* -------------------------------------------------------------------------------------------------*/ - -/* Configurate the protection feature to a given space. */ -bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window, - MEMORY_ACCESS gtMemoryAccess, - MEMORY_ACCESS_WRITE gtMemoryWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, - unsigned int size); - -/* Configurate the protection feature to a given space. */ -/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region, - MEMORY_ACCESS memoryAccess, - MEMORY_ACCESS_WRITE memoryWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, - unsigned int regionLength); */ -/* Configurate the snoop feature to a given space. */ -bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, - MEMORY_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); - -bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue); -bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); -bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); -/* Set a new base and size for one of the PCI windows. */ -bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase, - unsigned int pciWindowSize); - -/* Disable or enable one of the 21 windows dedicated for the CPU's - address decoding mechanism */ -void MemoryDisableWindow(MEMORY_WINDOW window); -void MemoryEnableWindow (MEMORY_WINDOW window); -MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window); -#endif /* __INCmemoryh */ diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h deleted file mode 100644 index 572e0d3..0000000 --- a/board/Marvell/include/pci.h +++ /dev/null @@ -1,293 +0,0 @@ -/* PCI.h - PCI functions header file */ - -/* Copyright - Galileo technology. */ - -#ifndef __INCpcih -#define __INCpcih - -/* includes */ - -#include "core.h" -#include "memory.h" - -/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */ -#define PCI_MAX_DEVICES 22 - - -/* Macros */ - -/* The next Macros configurate the initiator board (SELF) or any any agent on - the PCI to become: MASTER, response to MEMORY transactions , response to - IO transactions or TWO both MEMORY_IO transactions. Those configuration - are for both PCI0 and PCI1. */ - -#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \ - pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \ - pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \ - pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \ - pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber)) - -#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \ - pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \ - pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define MASTER_ENABLE BIT2 -#define MEMORY_ENABLE BIT1 -#define I_O_ENABLE BIT0 -#define SELF 32 - -/* Agent on the PCI bus may have up to 6 BARS. */ -#define BAR0 0x10 -#define BAR1 0x14 -#define BAR2 0x18 -#define BAR3 0x1c -#define BAR4 0x20 -#define BAR5 0x24 -#define BAR_SEL_MEM_IO BIT0 -#define BAR_MEM_TYPE_32_BIT NO_BIT -#define BAR_MEM_TYPE_BELOW_1M BIT1 -#define BAR_MEM_TYPE_64_BIT BIT2 -#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2) -#define BAR_MEM_TYPE_MASK (BIT1 | BIT2) -#define BAR_PREFETCHABLE BIT3 -#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3) - -/* Defines for the access regions. */ -#define PREFETCH_ENABLE BIT12 -#define PREFETCH_DISABLE NO_BIT -#define DELAYED_READ_ENABLE BIT13 -/* #define CACHING_ENABLE BIT14 */ -/* aggressive prefetch: PCI slave prefetch two burst in advance*/ -#define AGGRESSIVE_PREFETCH BIT16 -/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/ -#define READ_LINE_AGGRESSIVE_PREFETCH BIT17 -/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/ -#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18 -#define MAX_BURST_4 NO_BIT -#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */ -#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */ -#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */ -#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */ -#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */ -#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */ -#define PCI_ACCESS_PROTECT BIT28 -#define PCI_WRITE_PROTECT BIT29 - -/* typedefs */ - -typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5, - REGION6,REGION7} PCI_ACCESS_REGIONS; - -typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO; -typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK; - -typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB} - PCI_SNOOP_TYPE; -typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1, - PCI_SNOOP_REGION2,PCI_SNOOP_REGION3} - PCI_SNOOP_REGION; - -typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST; -typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1, - PCI_REGION2,PCI_REGION3, - PCI_IO} - PCI_REGION; - -/*ronen 7/Dec/03 */ -typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR, - PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR, - PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR, - PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR, - PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR, - PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR, - PCI_LAST_BAR} PCI_INTERNAL_BAR; - -typedef struct pciBar { - unsigned int detectBase; - unsigned int base; - unsigned int size; - unsigned int type; -} PCI_BAR; - -typedef struct pciDevice { - PCI_HOST host; - char type[40]; - unsigned int deviceNum; - unsigned int venID; - unsigned int deviceID; - PCI_BAR bar[6]; -} PCI_DEVICE; - -typedef struct pciSelfBars { - unsigned int SCS0Base; - unsigned int SCS0Size; - unsigned int SCS1Base; - unsigned int SCS1Size; - unsigned int SCS2Base; - unsigned int SCS2Size; - unsigned int SCS3Base; - unsigned int SCS3Size; - unsigned int internalMemBase; - unsigned int internalIOBase; - unsigned int CS0Base; - unsigned int CS0Size; - unsigned int CS1Base; - unsigned int CS1Size; - unsigned int CS2Base; - unsigned int CS2Size; - unsigned int CS3Base; - unsigned int CS3Size; - unsigned int CSBootBase; - unsigned int CSBootSize; - unsigned int P2PMem0Base; - unsigned int P2PMem0Size; - unsigned int P2PMem1Base; - unsigned int P2PMem1Size; - unsigned int P2PIOBase; - unsigned int P2PIOSize; - unsigned int CPUBase; - unsigned int CPUSize; -} PCI_SELF_BARS; - -/* read/write configuration registers on local PCI bus. */ -void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data); -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum); - -/* read/write configuration registers on another PCI bus. */ -void pciOverBridgeWriteConfigReg(PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum,unsigned int data); -unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum); - -/* Performs full scane on both PCI and returns all detail possible on the - agents which exist on the bus. */ -void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect, - unsigned int numberOfElment); - -/* Master`s memory space */ -bool pciMapSpace(PCI_HOST host, PCI_REGION region, - unsigned int remapBase, - unsigned int deviceBase, - unsigned int deviceLength); -unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region); -unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region); - -/* Slave`s memory space */ -void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, - unsigned int pci0Dram0Base, unsigned int pci0Dram0Size); - -#if 0 /* GARBAGE routines - dont use till they get cleaned up */ -void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars); -void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars); -void pci0MapInternalRegSpace(unsigned int pci0InternalBase); -void pci1MapInternalRegSpace(unsigned int pci1InternalBase); -void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase); -void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase); -void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base, - unsigned int pci0Dev0Length); -void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base, - unsigned int pci1Dev0Length); -void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base, - unsigned int pci0Dev1Length); -void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base, - unsigned int pci1Dev1Length); -void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base, - unsigned int pci0Dev2Length); -void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base, - unsigned int pci1Dev2Length); -void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base, - unsigned int pci0Dev3Length); -void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base, - unsigned int pci1Dev3Length); -void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase, - unsigned int pci0DevBootLength); -void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase, - unsigned int pci1DevBootLength); -void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base, - unsigned int pci0P2pMem0Length); -void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base, - unsigned int pci1P2pMem0Length); -void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base, - unsigned int pci0P2pMem1Length); -void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base, - unsigned int pci1P2pMem1Length); -void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase, - unsigned int pci0P2pIoLength); -void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase, - unsigned int pci1P2pIoLength); - -void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs); -void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs); -#endif - -/* PCI region options */ - -bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength); - -void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region); - -/* PCI arbiter */ - -bool pciArbiterEnable(PCI_HOST host); -bool pciArbiterDisable(PCI_HOST host); -bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5); -bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5); -bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5); -bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue); -bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue); - -/* PCI-to-PCI (P2P) */ - -bool pciP2PConfig(PCI_HOST host, - unsigned int SecondBusLow,unsigned int SecondBusHigh, - unsigned int busNum,unsigned int devNum); -/* PCI Cache-coherency */ - -bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); - -PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev); - -#endif /* __INCpcih */ diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c index ee1681b..55d0bc8 100644 --- a/board/a3m071/a3m071.c +++ b/board/a3m071/a3m071.c @@ -391,14 +391,14 @@ int misc_init_r(void) return 0; } -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); return 0; } -#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ #ifdef CONFIG_SPL_OS_BOOT /* diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c index c5d161b..20d8b80 100644 --- a/board/a4m072/a4m072.c +++ b/board/a4m072/a4m072.c @@ -170,14 +170,14 @@ void pci_init_board(void) } #endif -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); return 0; } -#endif +#endif /* CONFIG_OF_BOARD_SETUP */ int board_eth_init(bd_t *bis) { diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index c5cc4ff..dc2e3ba 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -489,7 +489,7 @@ int misc_init_r(void) } #endif /* !defined(CONFIG_ARCHES) */ -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP extern int __ft_board_setup(void *blob, bd_t *bd); int ft_board_setup(void *blob, bd_t *bd) @@ -518,4 +518,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 7b7cd2c..6398bcb 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -212,7 +212,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index af68e10..04e5812 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -191,7 +191,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; #ifndef CONFIG_SYS_NO_FLASH flash_size = 0; for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 4c64312..6871916 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -272,7 +272,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index d3555bb..fc4f50d 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -124,7 +124,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 9ef2864..994f246 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -151,7 +151,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index c14df30..b0d440d 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -196,7 +196,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/atmel/sama5d2_ptc/Kconfig b/board/atmel/sama5d2_ptc/Kconfig new file mode 100644 index 0000000..d2661c6 --- /dev/null +++ b/board/atmel/sama5d2_ptc/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D2_PTC + +config SYS_BOARD + default "sama5d2_ptc" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d2_ptc" + +endif diff --git a/board/atmel/sama5d2_ptc/MAINTAINERS b/board/atmel/sama5d2_ptc/MAINTAINERS new file mode 100644 index 0000000..7ab03d6 --- /dev/null +++ b/board/atmel/sama5d2_ptc/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D2 PTC Engineering BOARD +M: Wenyou Yang <wenyou.yang@atmel.com> +S: Maintained +F: board/atmel/sama5d2_ptc/ +F: include/configs/sama5d2_ptc.h +F: configs/sama5d2_ptc_spiflash_defconfig +F: configs/sama5d2_ptc_nandflash_defconfig diff --git a/board/atmel/sama5d2_ptc/Makefile b/board/atmel/sama5d2_ptc/Makefile new file mode 100644 index 0000000..1fe0392 --- /dev/null +++ b/board/atmel/sama5d2_ptc/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2016 Atmel +# Wenyou Yang <wenyou.yang@atmel.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d2_ptc.o diff --git a/board/atmel/sama5d2_ptc/sama5d2_ptc.c b/board/atmel/sama5d2_ptc/sama5d2_ptc.c new file mode 100644 index 0000000..9e6544b --- /dev/null +++ b/board/atmel/sama5d2_ptc/sama5d2_ptc.c @@ -0,0 +1,285 @@ +/* + * Copyright (C) 2016 Atmel + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <atmel_hlcdc.h> +#include <lcd.h> +#include <mmc.h> +#include <net.h> +#include <netdev.h> +#include <spi.h> +#include <version.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_usba_udc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5_sfr.h> +#include <asm/arch/sama5d2.h> +#include <asm/arch/sama5d3_smc.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); +} + +static void board_spi0_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0); + + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); + + at91_periph_clk_enable(ATMEL_ID_SPI0); +} + +static void board_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + + at91_periph_clk_enable(ATMEL_ID_HSMC); + + writel(AT91_SFR_EBICFG_DRIVE0_HIGH | + AT91_SFR_EBICFG_PULL0_NONE | + AT91_SFR_EBICFG_DRIVE1_HIGH | + AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) | + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0); /* D0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0); /* D1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0); /* D2 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0); /* D3 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0); /* D4 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0); /* D5 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0); /* D6 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0); /* D7 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0); /* RE */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0); /* WE */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1); /* NCS */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1); /* RDY */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1); /* ALE */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1); /* CLE */ +} + +static void board_usb_hw_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1); +} + +static void board_gmac_hw_init(void) +{ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */ + + at91_periph_clk_enable(ATMEL_ID_GMAC); +} + +static void board_uart0_hw_init(void) +{ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ + + at91_periph_clk_enable(CONFIG_USART_ID); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + + board_uart0_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + board_spi0_hw_init(); +#endif +#ifdef CONFIG_NAND_ATMEL + board_nand_hw_init(); +#endif +#ifdef CONFIG_MACB + board_gmac_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + board_usb_hw_init(); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); + if (rc) + printf("GMAC register failed\n"); +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + + return rc; +} + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_SERIALFLASH + board_spi0_hw_init(); +#endif + +#ifdef CONFIG_SYS_USE_NANDFLASH + board_nand_hw_init(); +#endif +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS5 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_DIS_DLL | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->rtr = 0x511; + + ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | + (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); + + ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | + (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | + (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | + (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); + + ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | + (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); +} + +void mem_init(void) +{ + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + ddrc_conf(&ddrc_config); + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + at91_system_clk_enable(AT91_PMC_DDR); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE, + &mpddrc->rd_data_path); + + ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); + + writel(0x3, &mpddrc->cal_mr4); + writel(64, &mpddrc->tim_cal); +} + +void at91_pmc_init(void) +{ + at91_plla_init(AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(82) | + AT91_PMC_PLLXR_DIV(1)); + + at91_pllicpr_init(0); + + at91_mck_init(AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA); +} +#endif diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 10edf28..93df7ba 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -171,10 +171,11 @@ static void board_sdhci0_hw_init(void) atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0); /* SDMMC0_DAT7 */ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0); /* SDMMC0_RSTN */ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SDMMC0_VDDSEL */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SDMMC0_CD */ at91_periph_clk_enable(ATMEL_ID_SDMMC0); at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0, - GCK_CSS_PLLA_CLK, 1); + GCK_CSS_UPLL_CLK, 1); } static void board_sdhci1_hw_init(void) @@ -190,7 +191,7 @@ static void board_sdhci1_hw_init(void) at91_periph_clk_enable(ATMEL_ID_SDMMC1); at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1, - GCK_CSS_PLLA_CLK, 1); + GCK_CSS_UPLL_CLK, 1); } int board_mmc_init(bd_t *bis) diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index e8ee612..fa90270 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -207,7 +207,7 @@ void lcd_show_board_info(void) nand_size = 0; #ifdef CONFIG_NAND_ATMEL for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; #endif lcd_printf("%ld MB SDRAM, %lld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index f4eef96..23ec274 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -191,7 +191,7 @@ void lcd_show_board_info(void) nand_size = 0; #ifdef CONFIG_NAND_ATMEL for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; #endif lcd_printf("%ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index aee6217..72bad23 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -187,7 +187,7 @@ void lcd_show_board_info(void) nand_size = 0; #ifdef CONFIG_NAND_ATMEL for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; #endif lcd_printf("%ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c index 1704627..106be9b 100644 --- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -42,12 +42,12 @@ void pinmux_init(void) void gpio_early_init(void) { /* Turn on the alive signal */ - gpio_request(GPIO_PV2, "ALIVE"); - gpio_direction_output(GPIO_PV2, 1); + gpio_request(TEGRA_GPIO(V, 2), "ALIVE"); + gpio_direction_output(TEGRA_GPIO(V, 2), 1); /* Remove the reset on the external periph */ - gpio_request(GPIO_PI4, "nRST_PERIPH"); - gpio_direction_output(GPIO_PI4, 1); + gpio_request(TEGRA_GPIO(I, 4), "nRST_PERIPH"); + gpio_direction_output(TEGRA_GPIO(I, 4), 1); } void pmu_write(uchar reg, uchar data) @@ -73,8 +73,8 @@ void board_sdmmc_voltage_init(void) pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300)); /* Switch the power on */ - gpio_request(GPIO_PJ2, "EN_3V3_EMMC"); - gpio_direction_output(GPIO_PJ2, 1); + gpio_request(TEGRA_GPIO(J, 2), "EN_3V3_EMMC"); + gpio_direction_output(TEGRA_GPIO(J, 2), 1); } /* diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 9c86779..4fb36a2 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -23,8 +23,8 @@ #ifdef CONFIG_BOARD_EARLY_INIT_F void gpio_early_init(void) { - gpio_request(GPIO_PI4, NULL); - gpio_direction_output(GPIO_PI4, 1); + gpio_request(TEGRA_GPIO(I, 4), NULL); + gpio_direction_output(TEGRA_GPIO(I, 4), 1); } #endif diff --git a/board/bosch/shc/Kconfig b/board/bosch/shc/Kconfig new file mode 100644 index 0000000..c71af11 --- /dev/null +++ b/board/bosch/shc/Kconfig @@ -0,0 +1,87 @@ +if TARGET_AM335X_SHC + +config SYS_BOARD + default "shc" + +config SYS_VENDOR + default "bosch" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "am335x_shc" + +choice + prompt "enable different boot versions for the shc board" + default EMMC + help + Select the boot version of the shc board. + +config SHC_EMMC + bool "enable eMMC" + help + enable here the eMMC functionality on the bosch shc board. + +config SHC_ICT + bool "enable ICT" + help + enable here the ICT functionality on the bosch shc board + +config SHC_NETBOOT + bool "enable NETBOOT" + help + enable here the NETBOOT functionality on the bosch shc board + +config SHC_SDBOOT + bool "enable SDBOOT" + help + enable here the SDBOOT functionality on the bosch shc board + +endchoice + +choice + prompt "enable different board versions for the shc board" + default C3_SAMPLE + help + Select the board version of the shc board. + +config B_SAMPLE + bool "B Sample board version" + help + activate, if you want to build for the B sample version + of the bosch shc board + +config B2_SAMPLE + bool "B2 Sample board version" + help + activate, if you want to build for the B2 sample version + of the bosch shc board + +config C_SAMPLE + bool "C Sample board version" + help + activate, if you want to build for the C sample version + of the bosch shc board + +config C2_SAMPLE + bool "C2 Sample board version" + help + activate, if you want to build for the C2 sample version + of the bosch shc board + +config C3_SAMPLE + bool "C3 Sample board version" + help + activate, if you want to build for the C3 sample version + of the bosch shc board + +config SERIES + bool "Series board version" + help + activate, if you want to build for the Series version + of the bosch shc board + +endchoice + +endif diff --git a/board/bosch/shc/MAINTAINERS b/board/bosch/shc/MAINTAINERS new file mode 100644 index 0000000..ae3c035 --- /dev/null +++ b/board/bosch/shc/MAINTAINERS @@ -0,0 +1,11 @@ +SHC BOARD +M: Heiko Schocher <hs@denx.de> +S: Maintained +F: board/bosch/shc +F: include/configs/am335x_shc.h +F: configs/am335x_shc_defconfig +F: configs/am335x_shc_ict_defconfig +F: configs/am335x_shc_netboot_defconfig +F: configs/am335x_shc_prompt_defconfig +F: configs/am335x_shc_sdboot_defconfig +F: configs/am335x_shc_sdboot_prompt_defconfig diff --git a/board/bosch/shc/Makefile b/board/bosch/shc/Makefile new file mode 100644 index 0000000..4fec2bf --- /dev/null +++ b/board/bosch/shc/Makefile @@ -0,0 +1,10 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mux.o +obj-y += board.o diff --git a/board/bosch/shc/README b/board/bosch/shc/README new file mode 100644 index 0000000..2f206e0 --- /dev/null +++ b/board/bosch/shc/README @@ -0,0 +1,114 @@ +Summary +======= + +This document covers various features of the 'am335x_shc' build. + +Hardware +======== + +AM335X based board: + +I2C: ready +DRAM: 512 MiB +Enabling the D-Cache +MMC: OMAP SD/MMC: 0 @ 26 MHz, OMAP SD/MMC: 1 @ 26 MHz +Net: cpsw + +Following boot options are possible: + +2 Jumpers: + +Jumper 1 Jumper 2 Bootmode +off off eMMC boot +on off SD boot +off on Net boot + +Compiling +========= + +$ make am335x_shc_defconfig + HOSTCC scripts/basic/fixdep + HOSTCC scripts/kconfig/conf.o + SHIPPED scripts/kconfig/zconf.tab.c + SHIPPED scripts/kconfig/zconf.lex.c + SHIPPED scripts/kconfig/zconf.hash.c + HOSTCC scripts/kconfig/zconf.tab.o + HOSTLD scripts/kconfig/conf +# +# configuration written to .config +# +$ make -s all + +-> now you have the MLO and the u-boot.img file, you can put +on your SD card or eMMC. + +Configuring +=========== + +There are a lot of board versions and boot configurations, which +can be selected through "make menuconfig" + +ARM architecture ---> + enable different boot versions for the shc board (enable eMMC) ---> + (X) enable eMMC + ( ) enable ICT + ( ) enable NETBOOT + ( ) enable SDBOOT + + enable different board versions for the shc board (C3 Sample board version) ---> + ( ) B Sample board version + ( ) B2 Sample board version + ( ) C Sample board version + ( ) C2 Sample board version + (X) C3 Sample board version + ( ) Series board version + +Netboot +======= +- see also doc/SPL/README.am335x-network + +- set the jumper into netboot mode +- compile the U-boot sources with: + make am335x_shc_netboot_defconfig + make all +- copy the images into your tftp boot directory + cp spl/u-boot-spl.bin /tftpboot/.../u-boot-spl-restore.bin + cp u-boot.img /tftpboot/.../u-boot-restore.img +- power on the board, and you should get something like this: + +U-Boot SPL 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18) +#### NETBOOT #### +SHC +MPU reference clock runs at 6 MHz +Setting MPU clock to 594 MHz +Enabling Spread Spectrum of 18 permille for MPU +Trying to boot from net +Using default environment + +<ethaddr> not set. Validating first E-fuse MAC +cpsw +cpsw Waiting for PHY auto negotiation to complete... done +link up on port 0, speed 100, full duplex +BOOTP broadcast 1 +BOOTP broadcast 2 +DHCP client bound to address 192.168.20.91 (258 ms) +Using cpsw device +TFTP from server 192.168.1.1; our IP address is 192.168.20.91 +Filename 'shc/u-boot-restore.img'. +Load address: 0x807fffc0 +Loading: ################## + 1.2 MiB/s +done +Bytes transferred = 262480 (40150 hex) + + +U-Boot 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18 +0200) + + Watchdog enabled +I2C: ready +DRAM: 512 MiB +MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 +*** Warning - bad CRC, using default environment + +Net: cpsw +switch to partitions #0, OK diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c new file mode 100644 index 0000000..e90693f --- /dev/null +++ b/board/bosch/shc/board.c @@ -0,0 +1,648 @@ +/* + * board.c + * + * (C) Copyright 2016 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <power/tps65217.h> +#include <environment.h> +#include <watchdog.h> +#include <environment.h> +#include "mmc.h" +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SPL_BUILD) || \ + (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH)) +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; +#endif +static struct shc_eeprom __attribute__((section(".data"))) header; +static int shc_eeprom_valid; + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, + sizeof(header))) { + puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return -EIO; + } + + if (header.magic != HDR_MAGIC) { + printf("Incorrect magic number (0x%x) in EEPROM\n", + header.magic); + return -EIO; + } + + shc_eeprom_valid = 1; + + return 0; +} + +static void shc_request_gpio(void) +{ + gpio_request(LED_PWR_BL_GPIO, "LED PWR BL"); + gpio_request(LED_PWR_RD_GPIO, "LED PWR RD"); + gpio_request(RESET_GPIO, "reset"); + gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN"); + gpio_request(WIFI_RST_GPIO, "WIFI rst"); + gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst"); + gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst"); + gpio_request(ENOC_RST_GPIO, "ENOC rst"); +#if defined CONFIG_B_SAMPLE + gpio_request(LED_PWR_GN_GPIO, "LED PWR GN"); + gpio_request(LED_CONN_BL_GPIO, "LED CONN BL"); + gpio_request(LED_CONN_RD_GPIO, "LED CONN RD"); + gpio_request(LED_CONN_GN_GPIO, "LED CONN GN"); +#else + gpio_request(LED_LAN_BL_GPIO, "LED LAN BL"); + gpio_request(LED_LAN_RD_GPIO, "LED LAN RD"); + gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL"); + gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD"); + gpio_request(LED_PWM_GPIO, "LED PWM"); + gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst"); +#endif + gpio_request(BACK_BUTTON_GPIO, "Back button"); + gpio_request(FRONT_BUTTON_GPIO, "Front button"); +} + +/* + * Function which forces all installed modules into running state for ICT + * testing. Called by SPL. + */ +static void __maybe_unused force_modules_running(void) +{ + /* Wi-Fi power regulator enable - high = enabled */ + gpio_direction_output(WIFI_REGEN_GPIO, 1); + /* + * Wait for Wi-Fi power regulator to reach a stable voltage + * (soft-start time, max. 350 µs) + */ + __udelay(350); + + /* Wi-Fi module reset - high = running */ + gpio_direction_output(WIFI_RST_GPIO, 1); + + /* ZigBee reset - high = running */ + gpio_direction_output(ZIGBEE_RST_GPIO, 1); + + /* BidCos reset - high = running */ + gpio_direction_output(BIDCOS_RST_GPIO, 1); + +#if !defined(CONFIG_B_SAMPLE) + /* Z-Wave reset - high = running */ + gpio_direction_output(Z_WAVE_RST_GPIO, 1); +#endif + + /* EnOcean reset - low = running */ + gpio_direction_output(ENOC_RST_GPIO, 0); +} + +/* + * Function which forces all installed modules into reset - to be released by + * the OS, called by SPL + */ +static void __maybe_unused force_modules_reset(void) +{ + /* Wi-Fi module reset - low = reset */ + gpio_direction_output(WIFI_RST_GPIO, 0); + + /* Wi-Fi power regulator enable - low = disabled */ + gpio_direction_output(WIFI_REGEN_GPIO, 0); + + /* ZigBee reset - low = reset */ + gpio_direction_output(ZIGBEE_RST_GPIO, 0); + + /* BidCos reset - low = reset */ + /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/ + +#if !defined(CONFIG_B_SAMPLE) + /* Z-Wave reset - low = reset */ + gpio_direction_output(Z_WAVE_RST_GPIO, 0); +#endif + + /* EnOcean reset - high = reset*/ + gpio_direction_output(ENOC_RST_GPIO, 1); +} + +/* + * Function to set the LEDs in the state "Bootloader booting" + */ +static void __maybe_unused leds_set_booting(void) +{ +#if defined(CONFIG_B_SAMPLE) + + /* Turn all red LEDs on */ + gpio_direction_output(LED_PWR_RD_GPIO, 1); + gpio_direction_output(LED_CONN_RD_GPIO, 1); + +#else /* All other SHCs starting with B2-Sample */ + /* Set the PWM GPIO */ + gpio_direction_output(LED_PWM_GPIO, 1); + /* Turn all red LEDs on */ + gpio_direction_output(LED_PWR_RD_GPIO, 1); + gpio_direction_output(LED_LAN_RD_GPIO, 1); + gpio_direction_output(LED_CLOUD_RD_GPIO, 1); + +#endif +} + +/* + * Function to set the LEDs in the state "Bootloader error" + */ +static void leds_set_failure(int state) +{ +#if defined(CONFIG_B_SAMPLE) + /* Turn all blue and green LEDs off */ + gpio_set_value(LED_PWR_BL_GPIO, 0); + gpio_set_value(LED_PWR_GN_GPIO, 0); + gpio_set_value(LED_CONN_BL_GPIO, 0); + gpio_set_value(LED_CONN_GN_GPIO, 0); + + /* Turn all red LEDs to 'state' */ + gpio_set_value(LED_PWR_RD_GPIO, state); + gpio_set_value(LED_CONN_RD_GPIO, state); + +#else /* All other SHCs starting with B2-Sample */ + /* Set the PWM GPIO */ + gpio_direction_output(LED_PWM_GPIO, 1); + + /* Turn all blue LEDs off */ + gpio_set_value(LED_PWR_BL_GPIO, 0); + gpio_set_value(LED_LAN_BL_GPIO, 0); + gpio_set_value(LED_CLOUD_BL_GPIO, 0); + + /* Turn all red LEDs to 'state' */ + gpio_set_value(LED_PWR_RD_GPIO, state); + gpio_set_value(LED_LAN_RD_GPIO, state); + gpio_set_value(LED_CLOUD_RD_GPIO, state); +#endif +} + +/* + * Function to set the LEDs in the state "Bootloader finished" + */ +static void leds_set_finish(void) +{ +#if defined(CONFIG_B_SAMPLE) + /* Turn all LEDs off */ + gpio_set_value(LED_PWR_BL_GPIO, 0); + gpio_set_value(LED_PWR_RD_GPIO, 0); + gpio_set_value(LED_PWR_GN_GPIO, 0); + gpio_set_value(LED_CONN_BL_GPIO, 0); + gpio_set_value(LED_CONN_RD_GPIO, 0); + gpio_set_value(LED_CONN_GN_GPIO, 0); +#else /* All other SHCs starting with B2-Sample */ + /* Turn all LEDs off */ + gpio_set_value(LED_PWR_BL_GPIO, 0); + gpio_set_value(LED_PWR_RD_GPIO, 0); + gpio_set_value(LED_LAN_BL_GPIO, 0); + gpio_set_value(LED_LAN_RD_GPIO, 0); + gpio_set_value(LED_CLOUD_BL_GPIO, 0); + gpio_set_value(LED_CLOUD_RD_GPIO, 0); + + /* Turn off the PWM GPIO and mux it to EHRPWM */ + gpio_set_value(LED_PWM_GPIO, 0); + enable_shc_board_pwm_pin_mux(); +#endif +} + +static void check_button_status(void) +{ + ulong value; + gpio_direction_input(FRONT_BUTTON_GPIO); + value = gpio_get_value(FRONT_BUTTON_GPIO); + + if (value == 0) { + printf("front button activated !\n"); + setenv("harakiri", "1"); + } +} + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 1; +} +#endif + +static void shc_board_early_init(void) +{ + shc_request_gpio(); +# ifdef CONFIG_SHC_ICT + /* Force all modules into enabled state for ICT testing */ + force_modules_running(); +# else + /* Force all modules to enter Reset state until released by the OS */ + force_modules_reset(); +# endif + leds_set_booting(); +} + +#define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */ +#define OSC (V_OSCK/1000000) +/* Bosch: Predivider must be fixed to 4, so N = 4-1 */ +#define MPUPLL_N (4-1) +/* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */ +#define MPUPLL_FREF (OSC / (MPUPLL_N + 1)) + +const struct dpll_params dpll_ddr_shc = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr_shc; +} + +/* + * As we enabled downspread SSC with 1.8%, the values needed to be corrected + * such that the 20% overshoot will not lead to too high frequencies. + * In all cases, this is achieved by subtracting one from M (6 MHz less). + * Example: 600 MHz CPU + * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz + * 600 MHz - 6 MHz (1x Fref) = 594 MHz + * SSC: 594 MHz * 1.8% = 10.7 MHz SSC + * Overshoot: 10.7 MHz * 20 % = 2.2 MHz + * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK! + */ +const struct dpll_params dpll_mpu_shc_opp100 = { + 99, MPUPLL_N, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + int sil_rev; + int mpu_vdd; + + puts(BOARD_ID_STR); + + /* + * Set CORE Frequency to OPP100 + * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100) + */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + sil_rev = readl(&cdev->deviceid) >> 28; + if (sil_rev < 2) { + puts("We do not support Silicon Revisions below 2.0!\n"); + return; + } + + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + if (i2c_probe(TPS65217_CHIP_PM)) + return; + + /* + * Retrieve the CPU max frequency by reading the efuse + * SHC-Default: 600 MHz + */ + switch (dpll_mpu_opp100.m) { + case MPUPLL_M_1000: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + break; + case MPUPLL_M_800: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + break; + case MPUPLL_M_720: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV; + break; + case MPUPLL_M_600: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV; + break; + case MPUPLL_M_300: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV; + break; + default: + puts("Cannot determine the frequency, failing!\n"); + return; + } + + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set MPU Frequency to what we detected */ + printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF); + printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF * + dpll_mpu_shc_opp100.m); + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100); + + /* Enable Spread Spectrum for this freq to be clean on EMI side */ + set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE); + + /* + * Using the default voltages for the PMIC (TPS65217D) + * LS1 = 1.8V (VDD_1V8) + * LS2 = 3.3V (VDD_3V3A) + * LDO1 = 1.8V (VIO and VRTC) + * LDO2 = 3.3V (VDD_3V3AUX) + */ + shc_board_early_init(); +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_shc_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs_evmsk = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +static const struct ddr_data ddr3_shc_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_shc_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_shc_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +void sdram_init(void) +{ + /* Configure the DDR3 RAM */ + config_ddr(400, &ioregs_evmsk, &ddr3_shc_data, + &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0); +} +#endif + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("EEPROM Content Invalid.\n"); + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#if defined(CONFIG_NOR) || defined(CONFIG_NAND) + gpmc_init(); +#endif + shc_request_gpio(); + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + check_button_status(); +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + if (shc_eeprom_valid) + if (is_valid_ethaddr(header.mac_addr)) + eth_setenv_enetaddr("ethaddr", header.mac_addr); +#endif + + return 0; +} +#endif + +#ifndef CONFIG_DM_ETH +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif + +/* + * This function will: + * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr + * in the environment + * Perform fixups to the PHY present on certain boards. We only need this + * function in: + * - SPL with either CPSW or USB ethernet support + * - Full U-Boot, with either CPSW or USB ethernet + * Build in only these cases to avoid warnings about unused variables + * when we build an SPL that has neither option but full U-Boot will. + */ +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \ + defined(CONFIG_SPL_USBETH_SUPPORT)) && \ + defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII; + cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if; + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + +#if defined(CONFIG_USB_ETHER) && \ + (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("usbnet_devaddr", mac_addr); + + rv = usb_eth_initialize(bis); + if (rv < 0) + printf("Error %d registering USB_ETHER\n", rv); + else + n += rv; +#endif + return n; +} +#endif + +#endif /* CONFIG_DM_ETH */ + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +static void bosch_check_reset_pin(void) +{ + if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) { + printf("Resetting ...\n"); + writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0); + disable_interrupts(); + reset_cpu(0); + /*NOTREACHED*/ + } +} + +static void hang_bosch(const char *cause, int code) +{ + int lv; + + gpio_direction_input(RESET_GPIO); + + /* Enable reset pin interrupt on falling edge */ + writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0); + writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT); + enable_interrupts(); + + puts(cause); + for (;;) { + for (lv = 0; lv < code; lv++) { + bosch_check_reset_pin(); + leds_set_failure(1); + __udelay(150 * 1000); + leds_set_failure(0); + __udelay(150 * 1000); + } +#if defined(BLINK_CODE) + __udelay(300 * 1000); +#endif + } +} + +void show_boot_progress(int val) +{ + switch (val) { + case BOOTSTAGE_ID_NEED_RESET: + hang_bosch("need reset", 4); + break; + } +} +#endif + +void arch_preboot_os(void) +{ + leds_set_finish(); +} + +#if defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* Bosch: Do not enable 52MHz for eMMC device to avoid EMI */ + ret = omap_mmc_init(0, MMC_MODE_HS_52MHz, 26000000, -1, -1); + if (ret) + return ret; + + ret = omap_mmc_init(1, MMC_MODE_HS_52MHz, 26000000, -1, -1); + return ret; +} +#endif diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h new file mode 100644 index 0000000..46167fe --- /dev/null +++ b/board/bosch/shc/board.h @@ -0,0 +1,187 @@ +/* + * board.h + * + * (C) Copyright 2016 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* Definition to control the GPIOs (for LEDs and Reset) */ +#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) + +static inline int board_is_b_sample(void) +{ +#if defined CONFIG_B_SAMPLE + return 1; +#else + return 0; +#endif +} + +static inline int board_is_c_sample(void) +{ +#if defined CONFIG_C_SAMPLE + return 1; +#else + return 0; +#endif +} + +static inline int board_is_c3_sample(void) +{ +#if defined CONFIG_C3_SAMPLE + return 1; +#else + return 0; +#endif +} + +static inline int board_is_series(void) +{ +#if defined CONFIG_SERIES + return 1; +#else + return 0; +#endif +} + +/* + * Definitions for pinmuxing header and Board ID strings + */ +#if defined CONFIG_B_SAMPLE +# define BOARD_ID_STR "SHC B-Sample\n" +#elif defined CONFIG_B2_SAMPLE +# define BOARD_ID_STR "SHC B2-Sample\n" +#elif defined CONFIG_C_SAMPLE +# if defined(CONFIG_SHC_NETBOOT) +# define BOARD_ID_STR "#### NETBOOT ####\nSHC C-Sample\n" +# elif defined(CONFIG_SHC_SDBOOT) +# define BOARD_ID_STR "#### SDBOOT ####\nSHC C-Sample\n" +# else +# define BOARD_ID_STR "SHC C-Sample\n" +# endif +#elif defined CONFIG_C2_SAMPLE +# if defined(CONFIG_SHC_ICT) +# define BOARD_ID_STR "#### ICT ####\nSHC C2-Sample\n" +# elif defined(CONFIG_SHC_NETBOOT) +# define BOARD_ID_STR "#### NETBOOT ####\nSHC C2-Sample\n" +# elif defined(CONFIG_SHC_SDBOOT) +# define BOARD_ID_STR "#### SDBOOT ####\nSHC C2-Sample\n" +# else +# define BOARD_ID_STR "SHC C2-Sample\n" +# endif +#elif defined CONFIG_C3_SAMPLE +# if defined(CONFIG_SHC_ICT) +# define BOARD_ID_STR "#### ICT ####\nSHC C3-Sample\n" +# elif defined(CONFIG_SHC_NETBOOT) +# define BOARD_ID_STR "#### NETBOOT ####\nSHC C3-Sample\n" +# elif defined(CONFIG_SHC_SDBOOT) +# define BOARD_ID_STR "#### SDBOOT ####\nSHC C3-Sample\n" +# else +# define BOARD_ID_STR "SHC C3-Sample\n" +# endif +#elif defined CONFIG_SERIES +# if defined(CONFIG_SHC_ICT) +# define BOARD_ID_STR "#### ICT ####\nSHC\n" +# elif defined(CONFIG_SHC_NETBOOT) +# define BOARD_ID_STR "#### NETBOOT ####\nSHC\n" +# elif defined(CONFIG_SHC_SDBOOT) +# define BOARD_ID_STR "#### SDBOOT ####\nSHC\n" +# else +# define BOARD_ID_STR "SHC\n" +# endif +#else +# define BOARD_ID_STR "Unknown device!\n" +#endif + +/* + * Definitions for GPIO pin assignments + */ +#if defined CONFIG_B_SAMPLE + +# define LED_PWR_BL_GPIO GPIO_TO_PIN(1, 17) +# define LED_PWR_RD_GPIO GPIO_TO_PIN(1, 18) +# define LED_PWR_GN_GPIO GPIO_TO_PIN(1, 19) +# define LED_CONN_BL_GPIO GPIO_TO_PIN(0, 26) +# define LED_CONN_RD_GPIO GPIO_TO_PIN(0, 22) +# define LED_CONN_GN_GPIO GPIO_TO_PIN(0, 23) +# define RESET_GPIO GPIO_TO_PIN(1, 29) +# define WIFI_REGEN_GPIO GPIO_TO_PIN(1, 16) +# define WIFI_RST_GPIO GPIO_TO_PIN(0, 27) +# define ZIGBEE_RST_GPIO GPIO_TO_PIN(3, 18) +# define BIDCOS_RST_GPIO GPIO_TO_PIN(0, 12) +# define ENOC_RST_GPIO GPIO_TO_PIN(1, 22) + +#else + +# define LED_PWR_BL_GPIO GPIO_TO_PIN(0, 22) +# define LED_PWR_RD_GPIO GPIO_TO_PIN(0, 23) +# define LED_LAN_BL_GPIO GPIO_TO_PIN(1, 17) +# define LED_LAN_RD_GPIO GPIO_TO_PIN(0, 26) +# define LED_CLOUD_BL_GPIO GPIO_TO_PIN(1, 18) +# define LED_CLOUD_RD_GPIO GPIO_TO_PIN(2, 2) +# define LED_PWM_GPIO GPIO_TO_PIN(1, 19) +# define RESET_GPIO GPIO_TO_PIN(1, 29) +# define WIFI_REGEN_GPIO GPIO_TO_PIN(1, 16) +# define WIFI_RST_GPIO GPIO_TO_PIN(0, 27) +# define ZIGBEE_RST_GPIO GPIO_TO_PIN(3, 18) +# define BIDCOS_RST_GPIO GPIO_TO_PIN(1, 24) +# define Z_WAVE_RST_GPIO GPIO_TO_PIN(1, 21) +# define ENOC_RST_GPIO GPIO_TO_PIN(1, 22) + +#endif + +#define BACK_BUTTON_GPIO GPIO_TO_PIN(1, 29) +#define FRONT_BUTTON_GPIO GPIO_TO_PIN(1, 25) + +/* Reset is on GPIO pin 29 of GPIO bank 1 */ +#define RESET_MASK (0x1 << 29) + +#define HDR_MAGIC 0x43485342 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 +#define HDR_REV_LEN 8 +#define HDR_SER_LEN 16 +#define HDR_ROOT_LEN 12 +#define HDR_FATC_LEN 12 + +/* +* SHC parameters held in On-Board I²C EEPROM device. +* +* Header Format +* +* Name Size Contents +*------------------------------------------------------------- +* Magic 4 0x42 0x53 0x48 0x43 [BSHC] +* +* Version 2 0x0100 for v1.0 +* +* Lenght 2 The length of the complete structure, not only this header +* +* Eth-MAC 6 Ethernet MAC Address +* SHC Pool: 7C:AC:B2:00:10:01 - TBD +* +* --- Further values follow, not important for Bootloader --- +*/ + +struct shc_eeprom { + u32 magic; + u16 version; + u16 lenght; + uint8_t mac_addr[HDR_ETH_ALEN]; +}; + +void enable_uart0_pin_mux(void); +void enable_shc_board_pin_mux(void); +void enable_shc_board_pwm_pin_mux(void); + +#endif diff --git a/board/bosch/shc/mux.c b/board/bosch/shc/mux.c new file mode 100644 index 0000000..e8ada65 --- /dev/null +++ b/board/bosch/shc/mux.c @@ -0,0 +1,261 @@ +/* + * mux.c + * + * (C) Copyright 2016 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */ + {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_CTS */ + {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)}, /* UART0_RTS */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)}, /* UART1_TXD */ + {OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART1_CTS */ + {OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)}, /* UART1_RTS */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux spi1_pin_mux[] = { + {OFFSET(mcasp0_aclkx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_SCLK */ + {OFFSET(mcasp0_fsx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D0 */ + {OFFSET(mcasp0_axr0), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D1 */ + {OFFSET(mcasp0_ahclkr), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_CS0 */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUP_EN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_CMD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDDIS)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUDDIS)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {-1}, +}; + +static struct module_pin_mux mmc2_pin_mux[] = { + {OFFSET(gpmc_ad12), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT0 */ + {OFFSET(gpmc_ad13), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT1 */ + {OFFSET(gpmc_ad14), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT2 */ + {OFFSET(gpmc_ad15), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT3 */ + {OFFSET(gpmc_csn3), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CMD */ + {OFFSET(gpmc_clk), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CLK */ + {-1}, +}; +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux gpio0_7_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUP_EN)}, /* GPIO0_7 */ + {-1}, +}; + +static struct module_pin_mux jtag_pin_mux[] = { + {OFFSET(xdma_event_intr0), (MODE(6) | RXACTIVE | PULLUDDIS)}, + {OFFSET(xdma_event_intr1), (MODE(6) | RXACTIVE | PULLUDDIS)}, + {OFFSET(nresetin_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdo), (MODE(0) | PULLUP_EN)}, + {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ntrst), (MODE(0) | RXACTIVE)}, + {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)}, + {OFFSET(rsvd2), (MODE(0) | PULLUP_EN)}, + {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)}, + {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)}, + {OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(gpmc_ad8), (MODE(7) | PULLUDDIS)}, /* gpio0[22] - LED_PWR_BL (external pull-down) */ + {OFFSET(gpmc_ad9), (MODE(7) | PULLUDDIS)}, /* gpio0[23] - LED_PWR_RD (external pull-down) */ + {OFFSET(gpmc_ad10), (MODE(7) | PULLUDDIS)}, /* gpio0[26] - LED_LAN_RD (external pull-down) */ + {OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)}, /* gpio0[27] - #WIFI_RST (external pull-down) */ + {OFFSET(gpmc_a0), (MODE(7) | PULLUDDIS)}, /* gpio1[16] - WIFI_REGEN */ + {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS)}, /* gpio1[17] - LED_LAN_BL */ + {OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS)}, /* gpio1[18] - LED_Cloud_BL */ + {OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS)}, /* gpio1[19] - LED_PWM as GPIO */ + {OFFSET(gpmc_a4), (MODE(7))}, /* gpio1[20] - #eMMC_RST */ + {OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)}, /* gpio1[21] - #Z-Wave_RST */ + {OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)}, /* gpio1[22] - ENOC_RST */ + {OFFSET(gpmc_a7), (MODE(7) | PULLUP_EN)}, /* gpio1[23] - WIFI_MODE */ + {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[24] - #BIDCOS_RST */ + {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[25] - USR_BUTTON */ + {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[26] - #USB1_OC */ + {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[27] - BIDCOS_PROG */ + {OFFSET(gpmc_be1n), (MODE(7) | PULLUP_EN)}, /* gpio1[28] - ZIGBEE_PC7 */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[29] - RESET_BUTTON */ + {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS)}, /* gpio2[2] - LED_Cloud_RD */ + {OFFSET(gpmc_oen_ren), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* gpio2[3] - #WIFI_POR */ + {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, /* gpio2[4] - N/C */ + {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)}, /* gpio2[5] - EEPROM_WP */ + {OFFSET(lcd_data0), (MODE(7) | PULLUDDIS)}, /* gpio2[6] */ + {OFFSET(lcd_data1), (MODE(7) | PULLUDDIS)}, /* gpio2[7] */ + {OFFSET(lcd_data2), (MODE(7) | PULLUDDIS)}, /* gpio2[8] */ + {OFFSET(lcd_data3), (MODE(7) | PULLUDDIS)}, /* gpio2[9] */ + {OFFSET(lcd_data4), (MODE(7) | PULLUDDIS)}, /* gpio2[10] */ + {OFFSET(lcd_data5), (MODE(7) | PULLUDDIS)}, /* gpio2[11] */ + {OFFSET(lcd_data6), (MODE(7) | PULLUDDIS)}, /* gpio2[12] */ + {OFFSET(lcd_data7), (MODE(7) | PULLUDDIS)}, /* gpio2[13] */ + {OFFSET(lcd_data8), (MODE(7) | PULLUDDIS)}, /* gpio2[14] */ + {OFFSET(lcd_data9), (MODE(7) | PULLUDDIS)}, /* gpio2[15] */ + {OFFSET(lcd_data10), (MODE(7) | PULLUDDIS)}, /* gpio2[16] */ + {OFFSET(lcd_data11), (MODE(7) | PULLUDDIS)}, /* gpio2[17] */ + {OFFSET(lcd_data12), (MODE(7) | PULLUDDIS)}, /* gpio0[8] */ + {OFFSET(lcd_data13), (MODE(7) | PULLUDDIS)}, /* gpio0[9] */ + {OFFSET(lcd_data14), (MODE(7) | PULLUDDIS)}, /* gpio0[10] */ + {OFFSET(lcd_data15), (MODE(7) | PULLUDDIS)}, /* gpio0[11] */ + {OFFSET(lcd_vsync), (MODE(7) | PULLUDDIS)}, /* gpio2[22] */ + {OFFSET(lcd_hsync), (MODE(7) | PULLUDDIS)}, /* gpio2[23] */ + {OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)}, /* gpio2[24] */ + {OFFSET(lcd_ac_bias_en), (MODE(7) | PULLUDDIS)},/* gpio2[25] */ + {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS)}, /* gpio0[4] */ + {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, /* gpio0[5] */ + {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS)}, /* gpio3[18] - #ZIGBEE_RST */ + {OFFSET(mcasp0_fsr), (MODE(7)) | PULLUDDIS}, /* gpio3[19] - ZIGBEE_BOOT */ + {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, /* gpio3[19] - ZIGBEE_BOOT */ + {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE | PULLUP_EN)},/* gpio3[21] - ZIGBEE_PC5 */ + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, + {OFFSET(mii1_txen), MODE(0)}, + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, + {OFFSET(mii1_txd3), MODE(0)}, + {OFFSET(mii1_txd2), MODE(0)}, + {OFFSET(mii1_txd1), MODE(0) | RXACTIVE}, + {OFFSET(mii1_txd0), MODE(0) | RXACTIVE}, + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, + {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, + {-1}, +}; + +static struct module_pin_mux pwm_pin_mux[] = { + {OFFSET(gpmc_a3), (MODE(6) | PULLUDDIS)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_shc_board_pwm_pin_mux(void) +{ + configure_module_pin_mux(pwm_pin_mux); +} + +void enable_shc_board_pin_mux(void) +{ + /* Do board-specific muxes. */ + if (board_is_c3_sample() || board_is_series()) { + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(mmc1_pin_mux); + configure_module_pin_mux(mmc2_pin_mux); + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(gpio0_7_pin_mux); + configure_module_pin_mux(gpio_pin_mux); + configure_module_pin_mux(uart1_pin_mux); + configure_module_pin_mux(uart2_pin_mux); + configure_module_pin_mux(uart4_pin_mux); + configure_module_pin_mux(spi1_pin_mux); + configure_module_pin_mux(jtag_pin_mux); + } else { + puts("Unknown board, cannot configure pinmux."); + hang(); + } +} diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index 5276907..fce998d 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -237,7 +237,7 @@ static void compose_hostname(hw_id_t hw_id, char *buf) } -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +#ifdef CONFIG_OF_BOARD_SETUP /* * Update 'model' and 'memory' properties in the blob according to the module * that we are running on. @@ -255,7 +255,7 @@ static void ft_blob_update(void *blob, bd_t *bd) printf("ft_blob_update(): cannot set /model property err:%s\n", fdt_strerror(ret)); } -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ +#endif /* CONFIG_OF_BOARD_SETUP */ /* @@ -358,7 +358,7 @@ int last_stage_init(void) #endif /* CONFIG_LAST_STAGE_INIT */ -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); @@ -366,4 +366,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/congatec/conga-qeval20-qa3-e3845/.gitignore b/board/congatec/conga-qeval20-qa3-e3845/.gitignore new file mode 100644 index 0000000..6eb8a54 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/board/congatec/conga-qeval20-qa3-e3845/Makefile b/board/congatec/conga-qeval20-qa3-e3845/Makefile index 23b8748..b784510 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/Makefile +++ b/board/congatec/conga-qeval20-qa3-e3845/Makefile @@ -5,3 +5,4 @@ # obj-y += conga-qeval20-qa3.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl new file mode 100644 index 0000000..eace459 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} + +/* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */ diff --git a/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index a15a9ed..1b6c40f 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -106,11 +106,11 @@ int checkboard (void) return 0; } -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig index b813adb..448176d 100644 --- a/board/dbau1x00/Kconfig +++ b/board/dbau1x00/Kconfig @@ -9,6 +9,21 @@ config SYS_SOC config SYS_CONFIG_NAME default "dbau1x00" +config SYS_TEXT_BASE + default 0xbfc00000 + +config SYS_DCACHE_SIZE + default 16384 + +config SYS_DCACHE_LINE_SIZE + default 32 + +config SYS_ICACHE_SIZE + default 16384 + +config SYS_ICACHE_LINE_SIZE + default 32 + menu "dbau1x00 board options" choice diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c index f46936c..51ac10c 100644 --- a/board/esd/common/esd405ep_nand.c +++ b/board/esd/common/esd405ep_nand.c @@ -16,7 +16,7 @@ */ static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); if (ctrl & NAND_CTRL_CHANGE) { if ( ctrl & NAND_CLE ) out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE); diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index ca9a944..c510ab1 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -471,7 +471,7 @@ int pci_pre_init(struct pci_controller *hose) } #endif /* defined(CONFIG_PCI) */ -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { int rc; @@ -493,4 +493,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c index cda1d7b..656f0fa 100644 --- a/board/esd/mecp5123/mecp5123.c +++ b/board/esd/mecp5123/mecp5123.c @@ -198,11 +198,11 @@ int checkboard(void) return 0; } -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c index 24e4977..31ac728 100644 --- a/board/esd/pmc405de/pmc405de.c +++ b/board/esd/pmc405de/pmc405de.c @@ -300,7 +300,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { int rc; @@ -322,7 +322,7 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ #if defined(CONFIG_SYS_EEPROM_WREN) /* Input: <dev_addr> I2C address of EEPROM device to enable. diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 7e35c19..0d43505 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -882,7 +882,7 @@ int board_usb_cleanup(int index, enum usb_init_type init) } #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */ -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { int rc; @@ -903,4 +903,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile index 0acd2a9..673d2ea 100644 --- a/board/freescale/b4860qds/Makefile +++ b/board/freescale/b4860qds/Makefile @@ -5,11 +5,11 @@ # ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o else obj-y += b4860qds.o -obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o -obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_B4860QDS) += eth_b4860qds.o +obj-$(CONFIG_PCI) += pci.o endif obj-y += ddr.o diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index eb10a6f..31b186e 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -179,15 +179,13 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - #else dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + return dram_size; } diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c index 3f7cc03..fabc783 100644 --- a/board/freescale/b4860qds/spl.c +++ b/board/freescale/b4860qds/spl.c @@ -91,6 +91,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifndef CONFIG_SPL_NAND_BOOT env_init(); diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile index b26d3a1..8027750 100644 --- a/board/freescale/bsc9131rdb/Makefile +++ b/board/freescale/bsc9131rdb/Makefile @@ -13,15 +13,11 @@ endif endif ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - +obj-y += spl_minimal.o else - -obj-y += bsc9131rdb.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o -#obj-y += bsc9131rdb_mux.o - +obj-y += bsc9131rdb.o +obj-y += ddr.o endif + +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile index 2e4170f..5419335 100644 --- a/board/freescale/bsc9132qds/Makefile +++ b/board/freescale/bsc9132qds/Makefile @@ -13,14 +13,11 @@ endif endif ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - +obj-y += spl_minimal.o else - obj-y += bsc9132qds.o obj-y += ddr.o +endif + obj-y += law.o obj-y += tlb.o - -endif diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile index 818484a..93b3cba 100644 --- a/board/freescale/c29xpcie/Makefile +++ b/board/freescale/c29xpcie/Makefile @@ -11,15 +11,15 @@ endif endif ifdef MINIMAL -obj-y += spl_minimal.o tlb.o law.o +obj-y += spl_minimal.o else ifdef CONFIG_SPL_BUILD obj-y += spl.o endif - obj-y += c29xpcie.o obj-y += cpld.o obj-y += ddr.o +endif + obj-y += law.o obj-y += tlb.o -endif diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c index e325b4d..45f463f 100644 --- a/board/freescale/c29xpcie/c29xpcie.c +++ b/board/freescale/c29xpcie/c29xpcie.c @@ -122,7 +122,7 @@ void fdt_del_sec(void *blob, int offset) while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0", CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET - + offset * 0x20000)) >= 0) { + + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) { fdt_del_node(blob, nodeoff); offset++; } diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c index 3d31d41..d8d73c7 100644 --- a/board/freescale/c29xpcie/spl.c +++ b/board/freescale/c29xpcie/spl.c @@ -57,6 +57,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; /* relocate environment function pointers etc. */ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c index f434269..0abaffb 100644 --- a/board/freescale/common/ls102xa_stream_id.c +++ b/board/freescale/common/ls102xa_stream_id.c @@ -10,11 +10,14 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num) { - uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR; + void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; int i; + u32 icid; - for (i = 0; i < num; i++) - out_be32(scfg + id[i].offset, id[i].stream_id); + for (i = 0; i < num; i++) { + icid = (id[i].stream_id & 0xff) << 24; + out_be32((u32 *)(scfg + id[i].offset), icid); + } } void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size) @@ -28,6 +31,6 @@ void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size) else liodn = tbl[i].id[0]; - out_le32((uint32_t *)(tbl[i].reg_offset), liodn); + out_le32((u32 *)(tbl[i].reg_offset), liodn); } } diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 113295f..0db0ed6 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -14,6 +14,13 @@ #include <i2c.h> #include "qixis.h" +#ifndef QIXIS_LBMAP_BRDCFG_REG +/* + * For consistency with existing platforms + */ +#define QIXIS_LBMAP_BRDCFG_REG 0x00 +#endif + #ifdef CONFIG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg) { @@ -27,6 +34,7 @@ void qixis_write_i2c(unsigned int reg, u8 value) } #endif +#ifdef QIXIS_BASE u8 qixis_read(unsigned int reg) { void *p = (void *)QIXIS_BASE; @@ -40,6 +48,7 @@ void qixis_write(unsigned int reg, u8 value) out_8(p + reg, value); } +#endif u16 qixis_read_minor(void) { @@ -142,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap) { u8 reg; - reg = QIXIS_READ(brdcfg[0]); + reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap; - QIXIS_WRITE(brdcfg[0], reg); + QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg); } static void __maybe_unused set_rcw_src(int rcw_src) diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig new file mode 100644 index 0000000..a34521c --- /dev/null +++ b/board/freescale/ls1012afrdm/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1012AFRDM + +config SYS_BOARD + default "ls1012afrdm" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012afrdm" + +endif diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS new file mode 100644 index 0000000..842f86f --- /dev/null +++ b/board/freescale/ls1012afrdm/MAINTAINERS @@ -0,0 +1,6 @@ +LS1012AFRDM BOARD +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +S: Maintained +F: board/freescale/ls1012afrdm/ +F: include/configs/ls1012afrdm.h +F: configs/ls1012afrdm_qspi_defconfig diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile new file mode 100644 index 0000000..dbfa2ce --- /dev/null +++ b/board/freescale/ls1012afrdm/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012afrdm.o diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README new file mode 100644 index 0000000..181c461 --- /dev/null +++ b/board/freescale/ls1012afrdm/README @@ -0,0 +1,58 @@ +Overview +-------- +QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development +platform, with a complete debugging environment. The LS1012AFRDM board +supports the QorIQ LS1012A processor and is optimized to support the +high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. + + LS1012AFRDM board Overview + ----------------------- + - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s + - 2 SGMII 1G PHYs + - DDR Controller + - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s + operating at 1.35 V + - QSPI + - Onboard 512 Mbit QSPI flash memory running at speed up + to 108/54 MHz + - One high-speed USB 2.0/3.0 port, one USB 2.0 port + - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a + Micro-AB connector. + - USB 2.0 port is a debug port (CMSIS DAP) and is configured + as a Micro-AB device. + - I2C controller + - One I2C bus with connectivity to Arduino headers + - UART + - UART (Console): UART1 (Without flow control) for console + - ARM JTAG support + - ARM Cortex® 10-pin JTAG connector for LS1012A + - CMSIS DAP through K20 microcontroller + - SAI Audio interface + - One SAI port, SAI 2 with full duplex support + - Clocks + - 25 MHz crystal for LS1012A + - 8 MHz Crystal for K20 + - 24 MHz for SC16IS740IPW SPI to Dual UART bridge + - Power Supplies + - 5 V input supply from USB + - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and + other board interfaces + +Booting Options +--------------- +QSPI Flash 1 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c new file mode 100644 index 0000000..a94a458 --- /dev/null +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -0,0 +1,192 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <hwconfig.h> +#include <fsl_csu.h> +#include <environment.h> +#include <fsl_mmdc.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + +int checkboard(void) +{ + puts("Board: LS1012AFRDM "); + + return 0; +} + +void mmdc_init(void) +{ + struct mmdc_p_regs *mmdc = + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + /* configure timing parms */ + out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); + out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); + out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); + out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); + + /* other parms */ + out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); + out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); + out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); + out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); + + /* out of reset delays */ + out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); + + /* physical parms */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); + out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); + + /* Enable MMDC */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); + + /* dram init sequence: update MRs */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | + CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); + + /* dram init sequence: ZQCL */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, + CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, + FORCE_ZQ_AUTO_CALIBRATION); + + /* Calibrations now: wr lvl */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | + CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); + set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); + + mdelay(1); + + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + mdelay(1); + + /* Calibrations now: Read DQS gating calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, + AUTO_RD_DQS_GATING_CALIBRATION_EN, + AUTO_RD_DQS_GATING_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* Calibrations now: Read calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, + AUTO_RD_CALIBRATION_EN, + AUTO_RD_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* PD, SR */ + out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); + out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); + + /* refresh scheme */ + set_wait_for_bits_clear(&mmdc->mdref, + CONFIG_SYS_MMDC_CORE_REFRESH_CTL, + START_REFRESH); + + /* disable CON_REQ */ + out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); +} + +int dram_init(void) +{ + mmdc_init(); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig new file mode 100644 index 0000000..1257ec8 --- /dev/null +++ b/board/freescale/ls1012aqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1012AQDS + +config SYS_BOARD + default "ls1012aqds" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012aqds" + +endif diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS new file mode 100644 index 0000000..27c4aff --- /dev/null +++ b/board/freescale/ls1012aqds/MAINTAINERS @@ -0,0 +1,6 @@ +LS1012AQDS BOARD +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +S: Maintained +F: board/freescale/ls1012aqds/ +F: include/configs/ls1012aqds.h +F: configs/ls1012aqds_qspi_defconfig diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile new file mode 100644 index 0000000..0b813f9 --- /dev/null +++ b/board/freescale/ls1012aqds/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012aqds.o diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README new file mode 100644 index 0000000..dee4b30 --- /dev/null +++ b/board/freescale/ls1012aqds/README @@ -0,0 +1,59 @@ +Overview +-------- +QorIQ LS1012A Development System (LS1012AQDS) is a high-performance +development platform, with a complete debugging environment. +The LS1012AQDS board supports the QorIQ LS1012A processor and is +optimized to support the high-bandwidth DDR3L memory and +a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A +SoC overview. + +LS1012AQDS board Overview +----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + - QSPI Controller + - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to QSPI NOR flash memory (2 virtual banks) and the QSPI + emulator + - USB 3.0 + - One USB 3.0 controller with integrated PHY + - One high-speed USB 3.0 port + - USB 2.0 + - One USB 2.0 controller with ULPI interface + - Two enhanced secure digital host controllers: + - SDHC1 controller can be connected to onboard SDHC connector + - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices + - 2 I2C controllers + - One SATA onboard connectors + - UART + - 5 SAI + - One SAI port with audio codec SGTL5000: + • Provides MIC bias + • Provides headphone and line output + - One SAI port terminated at 2x6 header + - Three SAI Tx/Rx ports terminated at 2x3 headers + - ARM JTAG support + +Booting Options +--------------- +a) QSPI Flash Emu Boot +b) QSPI Flash 1 +c) QSPI Flash 2 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c new file mode 100644 index 0000000..71eea82 --- /dev/null +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -0,0 +1,234 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <fdt_support.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/fdt.h> +#include <asm/arch/soc.h> +#include <ahci.h> +#include <hwconfig.h> +#include <mmc.h> +#include <scsi.h> +#include <fm_eth.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <fsl_mmdc.h> +#include <spl.h> +#include <netdev.h> + +#include "../common/qixis.h" +#include "ls1012aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + +int checkboard(void) +{ + char buf[64]; + u8 sw; + + sw = QIXIS_READ(arch); + printf("Board Arch: V%d, ", sw >> 4); + printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); + + sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); + + if (sw & QIXIS_LBMAP_ALTBANK) + printf("flash: 2\n"); + else + printf("flash: 1\n"); + + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + return 0; +} + +void mmdc_init(void) +{ + struct mmdc_p_regs *mmdc = + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + /* configure timing parms */ + out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); + out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); + out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); + out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); + + /* other parms */ + out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); + out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); + out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); + out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); + + /* out of reset delays */ + out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); + + /* physical parms */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); + out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); + + /* Enable MMDC */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); + + /* dram init sequence: update MRs */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | + CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); + + /* dram init sequence: ZQCL */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, + CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, + FORCE_ZQ_AUTO_CALIBRATION); + + /* Calibrations now: wr lvl */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | + CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); + set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); + + mdelay(1); + + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + mdelay(1); + + /* Calibrations now: Read DQS gating calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, + AUTO_RD_DQS_GATING_CALIBRATION_EN, + AUTO_RD_DQS_GATING_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* Calibrations now: Read calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, + AUTO_RD_CALIBRATION_EN, + AUTO_RD_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* PD, SR */ + out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); + out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); + + /* refresh scheme */ + set_wait_for_bits_clear(&mmdc->mdref, + CONFIG_SYS_MMDC_CORE_REFRESH_CTL, + START_REFRESH); + + /* disable CON_REQ */ + out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); +} + +int dram_init(void) +{ + mmdc_init(); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + u8 mux_sdhc_cd = 0x80; + + i2c_set_bus_num(0); + + i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); + return 0; +} +#endif + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *) + CONFIG_SYS_CCI400_ADDR; + + /* Set CCI-400 control override register to enable barrier + * transaction */ + out_le32(&cci->ctrl_ord, + CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} +#endif diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h new file mode 100644 index 0000000..584f604 --- /dev/null +++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h @@ -0,0 +1,35 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043AQDS_QIXIS_H__ +#define __LS1043AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1043AQDS */ + +/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +/* BRDCFG2 - SD clock*/ +#define QIXIS_SDCLK1_100 0x0 +#define QIXIS_SDCLK1_125 0x1 +#define QIXIS_SDCLK1_165 0x2 +#define QIXIS_SDCLK1_100_SP 0x3 + +#endif diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig new file mode 100644 index 0000000..3f67c28 --- /dev/null +++ b/board/freescale/ls1012ardb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1012ARDB + +config SYS_BOARD + default "ls1012ardb" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012ardb" + +endif diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS new file mode 100644 index 0000000..79a2a7d --- /dev/null +++ b/board/freescale/ls1012ardb/MAINTAINERS @@ -0,0 +1,6 @@ +LS1012ARDB BOARD +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +S: Maintained +F: board/freescale/ls1012ardb/ +F: include/configs/ls1012ardb.h +F: configs/ls1012ardb_qspi_defconfig diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile new file mode 100644 index 0000000..05fa9d9 --- /dev/null +++ b/board/freescale/ls1012ardb/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012ardb.o diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README new file mode 100644 index 0000000..453b4329 --- /dev/null +++ b/board/freescale/ls1012ardb/README @@ -0,0 +1,54 @@ +Overview +-------- +QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance +development platform, with a complete debugging environment. +The LS1012ARDB board supports the QorIQ LS1012A processor and is +optimized to support the high-bandwidth DDR3L memory and +a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. + +LS1012ARDB board Overview +----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to + - QSPI NOR flash memory (2 virtual banks) + - the QSPI emulator.s + - USB 3.0 + - one high-speed USB 2.0/3.0 port. + - Two enhanced secure digital host controllers: + - SDHC1 controller can be connected to onboard SDHC connector + - SDHC2 controller: Three dual 1:4 mux/demux devices, + 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC, + SDIO WiFi, SPI, and Ardiuno shield + - 2 I2C controllers + - One SATA onboard connectors + - UART + - The LS1012A processor consists of two UART controllers, + out of which only UART1 is used on RDB. + - ARM JTAG support + +Booting Options +--------------- +a) QSPI Flash Emu Boot +b) QSPI Flash 1 +c) QSPI Flash 2 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c new file mode 100644 index 0000000..f69768d --- /dev/null +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -0,0 +1,224 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <hwconfig.h> +#include <ahci.h> +#include <mmc.h> +#include <scsi.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <environment.h> +#include <fsl_mmdc.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + +int checkboard(void) +{ + u8 in1; + + puts("Board: LS1012ARDB "); + + /* Initialize i2c early for Serial flash bank information */ + i2c_set_bus_num(0); + + if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) { + printf("Error reading i2c boot information!\n"); + return 0; /* Don't want to hang() on this error */ + } + + puts("Version"); + if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A) + puts(": RevA"); + else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B) + puts(": RevB"); + else + puts(": unknown"); + + printf(", boot from QSPI"); + if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU) + puts(": emu\n"); + else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1) + puts(": bank1\n"); + else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2) + puts(": bank2\n"); + else + puts("unknown\n"); + + return 0; +} + +void mmdc_init(void) +{ + struct mmdc_p_regs *mmdc = + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + /* configure timing parms */ + out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); + out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); + out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); + out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); + + /* other parms */ + out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); + out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); + out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); + out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); + + /* out of reset delays */ + out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); + + /* physical parms */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); + out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); + + /* Enable MMDC */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); + + /* dram init sequence: update MRs */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | + CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); + + /* dram init sequence: ZQCL */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, + CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, + FORCE_ZQ_AUTO_CALIBRATION); + + /* Calibrations now: wr lvl */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | + CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); + set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); + + mdelay(1); + + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + mdelay(1); + + /* Calibrations now: Read DQS gating calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, + AUTO_RD_DQS_GATING_CALIBRATION_EN, + AUTO_RD_DQS_GATING_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* Calibrations now: Read calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, + AUTO_RD_CALIBRATION_EN, + AUTO_RD_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* PD, SR */ + out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); + out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); + + /* refresh scheme */ + set_wait_for_bits_clear(&mmdc->mdref, + CONFIG_SYS_MMDC_CORE_REFRESH_CTL, + START_REFRESH); + + /* disable CON_REQ */ + out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); +} + +int dram_init(void) +{ + mmdc_init(); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h index f819c99..b39b561 100644 --- a/board/freescale/ls1021aqds/ddr.h +++ b/board/freescale/ls1021aqds/ddr.h @@ -31,21 +31,21 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ #ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,}, - {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, - {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 8, 0x090A0B0B, 0x0C0D0E0C,}, + {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, #elif defined(CONFIG_SYS_FSL_DDR3) - {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, - {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, #else #error DDR type not defined #endif diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README index a6fd7a3..913537d 100644 --- a/board/freescale/ls1043aqds/README +++ b/board/freescale/ls1043aqds/README @@ -8,41 +8,8 @@ debugging environment. LS1043A SoC Overview -------------------- -The LS1043A integrated multicore processor combines four ARM Cortex-A53 -processor cores with datapath acceleration optimized for L2/3 packet -processing, single pass security offload and robust traffic management -and quality of service. - -The LS1043A SoC includes the following function and features: - - Four 64-bit ARM Cortex-A53 CPUs - - 1 MB unified L2 Cache - - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving - support - - Data Path Acceleration Architecture (DPAA) incorporating acceleration the - the following functions: - - Packet parsing, classification, and distribution (FMan) - - Queue management for scheduling, packet sequencing, and congestion - management (QMan) - - Hardware buffer management for buffer allocation and de-allocation (BMan) - - Cryptography acceleration (SEC) - - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface - - Up to 1 x QSGMII - - Up to 4 x SGMII supporting 1000Mbps - - Up to 2 x SGMII supporting 2500Mbps - - Up to 2 x RGMII supporting 1000Mbps - - High-speed peripheral interfaces - - Three PCIe 2.0 controllers, one supporting x4 operation - - One serial ATA (SATA 3.0) controllers - - Additional peripheral interfaces - - Three high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Quad Serial Peripheral Interface (QSPI) Controller - - Serial peripheral interface (SPI) controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller supporting NAND and NOR flash - - QorIQ platform's trust architecture 2.1 +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A +SoC overview. LS1043AQDS board Overview ----------------------- diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 3d3c533..0fd835d 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -116,6 +116,7 @@ phys_size_t initdram(int board_type) dram_size = fsl_ddr_sdram(); #endif + erratum_a008850_post(); #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h index 8adb660..ad709ba 100644 --- a/board/freescale/ls1043aqds/ddr.h +++ b/board/freescale/ls1043aqds/ddr.h @@ -7,6 +7,8 @@ #ifndef __DDR_H__ #define __DDR_H__ +extern void erratum_a008850_post(void); + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; @@ -32,21 +34,21 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ #ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,}, - {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, - {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,}, + {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, #elif defined(CONFIG_SYS_FSL_DDR3) - {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, - {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, #else #error DDR type not defined #endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index fba6b88..7e47ef0 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -238,8 +238,8 @@ int board_early_init_f(void) out_be32(&scfg->rcwpmuxcr0, 0x3333); out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); usb_pwrfault = - (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) | (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif @@ -307,14 +307,6 @@ int misc_init_r(void) int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *) - CONFIG_SYS_CCI400_ADDR; - - /* Set CCI-400 control override register to enable barrier - * transaction */ - out_le32(&cci->ctrl_ord, - CCI400_CTRLORD_EN_BARRIER); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); board_retimer_init(); @@ -325,10 +317,6 @@ int board_init(void) #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif - -#ifdef CONFIG_ENV_IS_NOWHERE - gd->env_addr = (ulong)&default_environment[0]; -#endif return 0; } diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README index 0556e73..709ddbb 100644 --- a/board/freescale/ls1043ardb/README +++ b/board/freescale/ls1043ardb/README @@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. LS1043A SoC Overview -------------------- -The LS1043A integrated multicore processor combines four ARM Cortex-A53 -processor cores with datapath acceleration optimized for L2/3 packet -processing, single pass security offload and robust traffic management -and quality of service. - -The LS1043A SoC includes the following function and features: - - Four 64-bit ARM Cortex-A53 CPUs - - 1 MB unified L2 Cache - - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving - support - - Data Path Acceleration Architecture (DPAA) incorporating acceleration the - the following functions: - - Packet parsing, classification, and distribution (FMan) - - Queue management for scheduling, packet sequencing, and congestion - management (QMan) - - Hardware buffer management for buffer allocation and de-allocation (BMan) - - Cryptography acceleration (SEC) - - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface - - Up to 1 x QSGMII - - Up to 4 x SGMII supporting 1000Mbps - - Up to 2 x SGMII supporting 2500Mbps - - Up to 2 x RGMII supporting 1000Mbps - - High-speed peripheral interfaces - - Three PCIe 2.0 controllers, one supporting x4 operation - - One serial ATA (SATA 3.0) controllers - - Additional peripheral interfaces - - Three high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Quad Serial Peripheral Interface (QSPI) Controller - - Serial peripheral interface (SPI) controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller supporting NAND and NOR flash - - QorIQ platform's trust architecture 2.1 +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A +SoC overview. LS1043ARDB board Overview ----------------------- diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 78c2824..c645283 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value) /* Set the boot bank to the alternate bank */ void cpld_set_altbank(void) { + u16 reg = CPLD_CFG_RCW_SRC_NOR; u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); u8 reg7 = CPLD_READ(vbank); - CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL); + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; CPLD_WRITE(vbank, reg7); @@ -42,7 +50,21 @@ void cpld_set_altbank(void) /* Set the boot bank to the default bank */ void cpld_set_defbank(void) { - CPLD_WRITE(global_rst, 1); + u16 reg = CPLD_CFG_RCW_SRC_NOR; + u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(vbank, 0); + + CPLD_WRITE(system_rst, 1); } void cpld_set_nand(void) diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h index bd59c0e..cb175b5 100644 --- a/board/freescale/ls1043ardb/cpld.h +++ b/board/freescale/ls1043ardb/cpld.h @@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value); #define CPLD_SW_MUX_BANK_SEL 0x40 #define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_SEL_ALTBANK 0x04 +#define CPLD_CFG_RCW_SRC_NOR 0x025 #define CPLD_CFG_RCW_SRC_NAND 0x106 #define CPLD_CFG_RCW_SRC_SD 0x040 #endif diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 11bc0f2..1e2fd2e 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -177,6 +177,8 @@ phys_size_t initdram(int board_type) #else dram_size = fsl_ddr_sdram_size(); #endif + erratum_a008850_post(); + #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); #endif diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h index b17eb80..a77ddf3 100644 --- a/board/freescale/ls1043ardb/ddr.h +++ b/board/freescale/ls1043ardb/ddr.h @@ -6,6 +6,9 @@ #ifndef __DDR_H__ #define __DDR_H__ + +extern void erratum_a008850_post(void); + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; @@ -31,9 +34,9 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ #ifdef CONFIG_SYS_FSL_DDR4 - {1, 1666, 0, 6, 7, 0x07090800, 0x00000000,}, - {1, 1900, 0, 6, 7, 0x07090800, 0x00000000,}, - {1, 2200, 0, 6, 7, 0x07090800, 0x00000000,}, + {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,}, + {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,}, + {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,}, #endif {} }; diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index ec5fdbf..1436520 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -19,7 +19,6 @@ #include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> -#include <environment.h> #include <fsl_sec.h> #include "cpld.h" #ifdef CONFIG_U_QE @@ -31,12 +30,12 @@ DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { - static const char *freq[3] = {"100.00MHZ", "156.25MHZ"}; + static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; #ifndef CONFIG_SD_BOOT u8 cfg_rcw_src1, cfg_rcw_src2; - u32 cfg_rcw_src; + u16 cfg_rcw_src; #endif - u32 sd1refclk_sel; + u8 sd1refclk_sel; printf("Board: LS1043ARDB, boot from "); @@ -83,22 +82,12 @@ int board_early_init_f(void) int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - - /* - * Set CCI-400 control override register to enable barrier - * transaction - */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; #ifdef CONFIG_FSL_IFC init_final_memctl_regs(); #endif -#ifdef CONFIG_ENV_IS_NOWHERE - gd->env_addr = (ulong)&default_environment[0]; -#endif - #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif @@ -106,6 +95,8 @@ int board_init(void) #ifdef CONFIG_U_QE u_qe_init(); #endif + /* invert AQR105 IRQ pins polarity */ + out_be32(&scfg->intpcr, AQR105_IRQ_MASK); return 0; } diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index 7d3bfc8..0765326 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -1,5 +1,5 @@ LS2080A BOARD -M: Prabhakar Kushwaha <prabhakar@freescale.com> +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> S: Maintained F: board/freescale/ls2080aqds/ F: board/freescale/ls2080a/ls2080aqds.c diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index 6ddad92..5c98866 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -7,48 +7,9 @@ SW development platform for the Freescale LS2080A processor series, with a complete debugging environment. LS2080A SoC Overview ------------------- -The LS2080A integrated multicore processor combines eight ARM Cortex-A57 -processor cores with high-performance data path acceleration logic and network -and peripheral bus interfaces required for networking, telecom/datacom, -wireless infrastructure, and mil/aerospace applications. - -The LS2080A SoC includes the following function and features: - - - Eight 64-bit ARM Cortex-A57 CPUs - - 1 MB platform cache with ECC - - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support - - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by - the AIOP - - Data path acceleration architecture (DPAA2) incorporating acceleration for - the following functions: - - Packet parsing, classification, and distribution (WRIOP) - - Queue and Hardware buffer management for scheduling, packet sequencing, and - congestion management, buffer allocation and de-allocation (QBMan) - - Cryptography acceleration (SEC) at up to 10 Gbps - - RegEx pattern matching acceleration (PME) at up to 10 Gbps - - Decompression/compression acceleration (DCE) at up to 20 Gbps - - Accelerated I/O processing (AIOP) at up to 20 Gbps - - QDMA engine - - 16 SerDes lanes at up to 10.3125 GHz - - Ethernet interfaces - - Up to eight 10 Gbps Ethernet MACs - - Up to eight 1 / 2.5 Gbps Ethernet MACs - - High-speed peripheral interfaces - - Four PCIe 3.0 controllers, one supporting SR-IOV - - Additional peripheral interfaces - - Two serial ATA (SATA 3.0) controllers - - Two high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Serial peripheral interface (SPI) controller - - Quad Serial Peripheral Interface (QSPI) Controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash - - Support for hardware virtualization and partitioning enforcement - - QorIQ platform's trust architecture 3.0 - - Service processor (SP) provides pre-boot initialization and secure-boot - capabilities +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. LS2080AQDS board Overview ----------------------- diff --git a/board/freescale/ls2080aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h index b76ea61..eba62c3 100644 --- a/board/freescale/ls2080aqds/ddr.h +++ b/board/freescale/ls2080aqds/ddr.h @@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2300, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2300, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, {} }; @@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, - {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, + {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, + {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, {} }; @@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, {} }; @@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, {} }; diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index b3bd40a..897793d 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -282,7 +282,9 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { +#ifdef CONFIG_FSL_MC_ENET int err; +#endif u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS index 5562917..a20c003 100644 --- a/board/freescale/ls2080ardb/MAINTAINERS +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -1,5 +1,5 @@ LS2080A BOARD -M: Prabhakar Kushwaha <prabhakar@freescale.com> +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> S: Maintained F: board/freescale/ls2080ardb/ F: board/freescale/ls2080a/ls2080ardb.c diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README index 6708ca9..b1613ba 100644 --- a/board/freescale/ls2080ardb/README +++ b/board/freescale/ls2080ardb/README @@ -5,48 +5,9 @@ evaluation, and development platform that supports the QorIQ LS2080A Layerscape Architecture processor. LS2080A SoC Overview ------------------- -The LS2080A integrated multicore processor combines eight ARM Cortex-A57 -processor cores with high-performance data path acceleration logic and network -and peripheral bus interfaces required for networking, telecom/datacom, -wireless infrastructure, and mil/aerospace applications. - -The LS2080A SoC includes the following function and features: - - - Eight 64-bit ARM Cortex-A57 CPUs - - 1 MB platform cache with ECC - - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support - - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by - the AIOP - - Data path acceleration architecture (DPAA2) incorporating acceleration for - the following functions: - - Packet parsing, classification, and distribution (WRIOP) - - Queue and Hardware buffer management for scheduling, packet sequencing, and - congestion management, buffer allocation and de-allocation (QBMan) - - Cryptography acceleration (SEC) at up to 10 Gbps - - RegEx pattern matching acceleration (PME) at up to 10 Gbps - - Decompression/compression acceleration (DCE) at up to 20 Gbps - - Accelerated I/O processing (AIOP) at up to 20 Gbps - - QDMA engine - - 16 SerDes lanes at up to 10.3125 GHz - - Ethernet interfaces - - Up to eight 10 Gbps Ethernet MACs - - Up to eight 1 / 2.5 Gbps Ethernet MACs - - High-speed peripheral interfaces - - Four PCIe 3.0 controllers, one supporting SR-IOV - - Additional peripheral interfaces - - Two serial ATA (SATA 3.0) controllers - - Two high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Serial peripheral interface (SPI) controller - - Quad Serial Peripheral Interface (QSPI) Controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash - - Support for hardware virtualization and partitioning enforcement - - QorIQ platform's trust architecture 3.0 - - Service processor (SP) provides pre-boot initialization and secure-boot - capabilities +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. LS2080ARDB board Overview ----------------------- diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h index bda9d4a..8d5a490 100644 --- a/board/freescale/ls2080ardb/ddr.h +++ b/board/freescale/ls2080ardb/ddr.h @@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,}, - {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,}, - {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,}, + {2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,}, + {2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,}, {} }; @@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, - {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, + {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, + {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, {} }; @@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, {} }; @@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, {} }; diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index fb39af6..52e5e3f 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -156,7 +156,9 @@ int board_init(void) { char *env_hwconfig; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; +#ifdef CONFIG_FSL_MC_ENET u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; +#endif u32 val; init_final_memctl_regs(); @@ -178,8 +180,10 @@ int board_init(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); +#ifdef CONFIG_FSL_MC_ENET /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); +#endif return 0; } @@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { +#ifdef CONFIG_FSL_MC_ENET int err; +#endif u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index 8d88bc0..8849681 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index 92cef2a..a96a599 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 40bd55d..7c44282 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -274,11 +274,11 @@ int checkboard (void) return 0; } -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile index 660d1bb..86eb694 100644 --- a/board/freescale/p1010rdb/Makefile +++ b/board/freescale/p1010rdb/Makefile @@ -13,18 +13,14 @@ endif endif ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - +obj-y += spl_minimal.o else - ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o endif - obj-y += p1010rdb.o obj-y += ddr.o +endif + obj-y += law.o obj-y += tlb.o - -endif diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index eb8e567..f858408 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -72,6 +72,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifndef CONFIG_SPL_NAND_BOOT env_init(); diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile index a582127..9793853 100644 --- a/board/freescale/p1022ds/Makefile +++ b/board/freescale/p1022ds/Makefile @@ -13,17 +13,15 @@ endif endif ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - +obj-y += spl_minimal.o else ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o endif obj-y += p1022ds.o obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o - obj-$(CONFIG_FSL_DIU_FB) += diu.o endif + +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index 89ef95a..04db767 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -86,6 +86,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifndef CONFIG_SPL_NAND_BOOT env_init(); #endif diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile index a2a1f92..045d409 100644 --- a/board/freescale/p1_p2_rdb_pc/Makefile +++ b/board/freescale/p1_p2_rdb_pc/Makefile @@ -13,17 +13,14 @@ endif endif ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - +obj-y += spl_minimal.o else ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o endif - -obj-y += p1_p2_rdb_pc.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o - +obj-y += p1_p2_rdb_pc.o +obj-y += ddr.o endif + +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 0142746..76a3cf4 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -83,6 +83,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifndef CONFIG_SPL_NAND_BOOT env_init(); diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile index c74f4c6..a335ec6 100644 --- a/board/freescale/p2041rdb/Makefile +++ b/board/freescale/p2041rdb/Makefile @@ -7,6 +7,6 @@ # obj-y += p2041rdb.o -obj-y += cpld.o +obj-y += cpld.o obj-y += ddr.o obj-y += eth.o diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile index d94f230..afbc914 100644 --- a/board/freescale/t102xqds/Makefile +++ b/board/freescale/t102xqds/Makefile @@ -5,7 +5,7 @@ # ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o else obj-y += t102xqds.o obj-y += eth_t102xqds.o diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c index 2d4d10f..c26f350 100644 --- a/board/freescale/t102xqds/ddr.c +++ b/board/freescale/t102xqds/ddr.c @@ -35,18 +35,18 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ #if defined(CONFIG_SYS_FSL_DDR4) - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,}, #elif defined(CONFIG_SYS_FSL_DDR3) - {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, #else #error DDR type not defined #endif @@ -172,14 +172,13 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c index 073ff2d..d59d343 100644 --- a/board/freescale/t102xqds/spl.c +++ b/board/freescale/t102xqds/spl.c @@ -120,6 +120,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_NAND_BOOT nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile index 0520066..6452865 100644 --- a/board/freescale/t102xrdb/Makefile +++ b/board/freescale/t102xrdb/Makefile @@ -5,7 +5,7 @@ # ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o else obj-y += t102xrdb.o obj-$(CONFIG_T1024RDB) += cpld.o diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index adf9fd5..edfbdbf 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -34,12 +34,12 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, {} }; @@ -234,12 +234,12 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); #endif dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index da97c44..bd3cbbf 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -107,6 +107,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_NAND_BOOT nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index a6e1673..1e08746 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -29,18 +29,18 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ #ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,}, #elif defined(CONFIG_SYS_FSL_DDR3) - {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, #else #error DDR type not defined #endif diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index cf79d2d..22d6a5f 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -124,15 +124,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - #else dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h index b9c02f7..012991c 100644 --- a/board/freescale/t104xrdb/ddr.h +++ b/board/freescale/t104xrdb/ddr.h @@ -29,20 +29,20 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 */ #ifdef CONFIG_SYS_FSL_DDR4 - {2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a}, + {2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a}, #elif defined(CONFIG_SYS_FSL_DDR3) - {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, - {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, - {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, - {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, - {1, 833, 4, 4, 6, 0x06060607, 0x08080807}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807}, - {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, - {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {2, 833, 4, 8, 6, 0x06060607, 0x08080807}, + {2, 833, 0, 8, 6, 0x06060607, 0x08080807}, + {2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 833, 4, 8, 6, 0x06060607, 0x08080807}, + {1, 833, 0, 8, 6, 0x06060607, 0x08080807}, + {1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, #else #error DDR type not defined #endif diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index 81f48c4..4b35af6 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -98,6 +98,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_MMC_BOOT mmc_initialize(bd); diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS index deda092..d747de3 100644 --- a/board/freescale/t208xqds/MAINTAINERS +++ b/board/freescale/t208xqds/MAINTAINERS @@ -1,5 +1,5 @@ T208XQDS BOARD -#M: - +M: Shengzhou Liu <Shengzhou.Liu@nxp.com> S: Maintained F: board/freescale/t208xqds/ F: include/configs/T208xQDS.h diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile index 6cb72c9..ef04a26 100644 --- a/board/freescale/t208xqds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -7,10 +7,8 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else -obj-$(CONFIG_T2080QDS) += t208xqds.o -obj-$(CONFIG_T2080QDS) += eth_t208xqds.o -obj-$(CONFIG_T2081QDS) += t208xqds.o -obj-$(CONFIG_T2081QDS) += eth_t208xqds.o +obj-$(CONFIG_T2080QDS) += t208xqds.o eth_t208xqds.o +obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index f1aff54..f96470f 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -108,13 +108,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; return dram_size; } diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h index 9c26fdf..255ab2c 100644 --- a/board/freescale/t208xqds/ddr.h +++ b/board/freescale/t208xqds/ddr.h @@ -28,17 +28,17 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09}, - {2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a}, - {2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c}, - {2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d}, - {2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d}, - {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, - {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, - {1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c}, - {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09}, + {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a}, + {2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c}, + {2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d}, + {2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d}, + {1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b}, + {1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c}, + {1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b}, {} }; @@ -49,15 +49,15 @@ static const struct board_specific_parameters rdimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ /* TODO: need tuning these parameters if RDIMM is used */ - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, + {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, {} }; diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index 55a0f8f..bb02dab 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -106,6 +106,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_NAND_BOOT nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS index 1642879..ccbfbab 100644 --- a/board/freescale/t208xrdb/MAINTAINERS +++ b/board/freescale/t208xrdb/MAINTAINERS @@ -1,5 +1,5 @@ T208XRDB BOARD -#M: - +M: Shengzhou Liu <Shengzhou.Liu@nxp.com> S: Maintained F: board/freescale/t208xrdb/ F: include/configs/T208xRDB.h diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile index 9605f8b..cd8fe09 100644 --- a/board/freescale/t208xrdb/Makefile +++ b/board/freescale/t208xrdb/Makefile @@ -5,11 +5,9 @@ # ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o else -obj-$(CONFIG_T2080RDB) += t208xrdb.o -obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o -obj-$(CONFIG_T2080RDB) += cpld.o +obj-$(CONFIG_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c index 053f128..f6c8ca3 100644 --- a/board/freescale/t208xrdb/ddr.c +++ b/board/freescale/t208xrdb/ddr.c @@ -101,12 +101,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + return dram_size; } diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h index 08cbb60..175cf56 100644 --- a/board/freescale/t208xrdb/ddr.h +++ b/board/freescale/t208xrdb/ddr.h @@ -28,16 +28,16 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, - {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, - {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {2, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09}, - {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, - {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, - {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09}, + {2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09}, + {2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a}, + {2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09}, + {1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a}, + {1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09}, {} }; diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index f63366b..2ff05a2 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -76,6 +76,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_NAND_BOOT nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile index bd2c1f1..731ccb0 100644 --- a/board/freescale/t4qds/Makefile +++ b/board/freescale/t4qds/Makefile @@ -5,12 +5,12 @@ # ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o else -obj-$(CONFIG_T4240QDS) += t4240qds.o -obj-$(CONFIG_T4240QDS)+= eth.o +obj-$(CONFIG_T4240QDS) += t4240qds.o eth.o obj-$(CONFIG_PCI) += pci.o endif + obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 62d58c5..d533924 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -117,13 +117,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + return dram_size; } diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h index 4d0e3c4..0b0cc9a 100644 --- a/board/freescale/t4qds/ddr.h +++ b/board/freescale/t4qds/ddr.h @@ -31,16 +31,16 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, + {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, + {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, + {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, {} }; @@ -50,15 +50,15 @@ static const struct board_specific_parameters rdimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, + {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, + {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, + {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, {} }; diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c index d52059a..6ca0f03 100644 --- a/board/freescale/t4qds/spl.c +++ b/board/freescale/t4qds/spl.c @@ -116,6 +116,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_NAND_BOOT nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index 83b55ee..4f29eea 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -5,13 +5,14 @@ # ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o else -obj-$(CONFIG_T4240RDB) += t4240rdb.o -obj-y += cpld.o -obj-y += eth.o +obj-$(CONFIG_T4240RDB) += t4240rdb.o +obj-y += cpld.o +obj-y += eth.o obj-$(CONFIG_PCI) += pci.o endif + obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c index 27b37b5..230f031 100644 --- a/board/freescale/t4rdb/ddr.c +++ b/board/freescale/t4rdb/ddr.c @@ -110,13 +110,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; return dram_size; } diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h index 7b85476..f01ebb2 100644 --- a/board/freescale/t4rdb/ddr.h +++ b/board/freescale/t4rdb/ddr.h @@ -27,16 +27,16 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a}, - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b}, + {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a}, + {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09}, + {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b}, + {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a}, + {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, + {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, + {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a}, + {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a}, + {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b}, {} }; @@ -46,15 +46,15 @@ static const struct board_specific_parameters rdimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, + {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, {} }; diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index e563a61..ae2451e 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -77,6 +77,9 @@ int board_eth_init(bd_t *bis) puts("Invalid SerDes1 protocol for T4240RDB\n"); } + fm_disable_port(FM1_DTSEC5); + fm_disable_port(FM1_DTSEC6); + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { @@ -115,6 +118,8 @@ int board_eth_init(bd_t *bis) puts("Invalid SerDes2 protocol for T4240RDB\n"); } + fm_disable_port(FM2_DTSEC5); + fm_disable_port(FM2_DTSEC6); for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index 4c1e0cc..b148a7f 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -80,6 +80,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; mmc_initialize(bd); mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 82313e8..70395ac 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -743,7 +743,7 @@ int misc_init_r(void) return 0; } -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP static int ft_sethdmiinfmt(void *blob, char *mode) { @@ -996,7 +996,7 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ static struct mxc_serial_platdata ventana_mxc_serial_plat = { .reg = (struct mxc_uart *)UART2_BASE, diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index ce23045..d4f0e70 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o obj-$(CONFIG_STRIDER) += fanctrl.o obj-$(CONFIG_STRIDER_CON) += osd.o +obj-$(CONFIG_STRIDER_CON_DP) += osd.o diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c index 96f02d6..f72a01e 100644 --- a/board/gdsys/common/ioep-fpga.c +++ b/board/gdsys/common/ioep-fpga.c @@ -25,8 +25,9 @@ enum { enum { COMPRESSION_NONE = 0, - COMPRESSION_TYPE1_DELTA = 1, - COMPRESSION_TYPE1_TYPE2_DELTA = 3, + COMPRESSION_TYPE_1 = 1, + COMPRESSION_TYPE_1_2 = 3, + COMPRESSION_TYPE_1_2_3 = 7, }; enum { @@ -158,12 +159,16 @@ void ioep_fpga_print_info(unsigned int fpga) printf(" no compression"); break; - case COMPRESSION_TYPE1_DELTA: - printf(" type1-deltacompression"); + case COMPRESSION_TYPE_1: + printf(" compression type1(delta)"); break; - case COMPRESSION_TYPE1_TYPE2_DELTA: - printf(" type1-deltacompression, type2-inlinecompression"); + case COMPRESSION_TYPE_1_2: + printf(" compression type1(delta), type2(inline)"); + break; + + case COMPRESSION_TYPE_1_2_3: + printf(" compression type1(delta), type2(inline), type3(intempo)"); break; default: diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 4e292f5..add9574 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -469,6 +469,9 @@ int osd_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) { + if (!(osd_screen_mask & (1 << screen))) + continue; + OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1)); OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535); OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535); diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c index 8d01d8b..2d7d789 100644 --- a/board/gdsys/intip/intip.c +++ b/board/gdsys/intip/intip.c @@ -203,7 +203,7 @@ int misc_init_r(void) return 0; } -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP extern void __ft_board_setup(void *blob, bd_t *bd); int ft_board_setup(void *blob, bd_t *bd) @@ -218,4 +218,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c index eee582b..121977d 100644 --- a/board/gdsys/mpc8308/strider.c +++ b/board/gdsys/mpc8308/strider.c @@ -133,6 +133,9 @@ int last_stage_init(void) unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; #endif bool hw_type_cat = pca9698_get_value(0x20, 18); +#ifdef CONFIG_STRIDER_CON_DP + bool is_dh = pca9698_get_value(0x20, 25); +#endif bool ch0_sgmii2_present = false; /* Turn on Analog Devices ADV7611 */ @@ -140,6 +143,7 @@ int last_stage_init(void) /* Turn on Parade DP501 */ pca9698_direction_output(0x20, 10, 1); + pca9698_direction_output(0x20, 11, 1); ch0_sgmii2_present = !pca9698_get_value(0x20, 37); @@ -202,6 +206,14 @@ int last_stage_init(void) osd_probe(0); #endif +#ifdef CONFIG_STRIDER_CON_DP + if (ioep_fpga_has_osd(0)) { + osd_probe(0); + if (is_dh) + osd_probe(4); + } +#endif + #ifdef CONFIG_STRIDER_CPU ch7301_probe(0, false); dp501_probe(0, false); @@ -226,6 +238,13 @@ int last_stage_init(void) if (ioep_fpga_has_osd(k)) osd_probe(k); #endif +#ifdef CONFIG_STRIDER_CON_DP + if (ioep_fpga_has_osd(k)) { + osd_probe(k); + if (is_dh) + osd_probe(k + 4); + } +#endif #ifdef CONFIG_STRIDER_CPU if (!adv7611_probe(k)) printf(" Advantiv ADV7611 HDMI Receiver\n"); @@ -270,6 +289,24 @@ int fpga_gpio_get(unsigned int bus, int pin) return val & pin; } +#ifdef CONFIG_STRIDER_CON_DP +void fpga_control_set(unsigned int bus, int pin) +{ + u16 val; + + FPGA_GET_REG(bus, control, &val); + FPGA_SET_REG(bus, control, val | pin); +} + +void fpga_control_clear(unsigned int bus, int pin) +{ + u16 val; + + FPGA_GET_REG(bus, control, &val); + FPGA_SET_REG(bus, control, val & ~pin); +} +#endif + void mpc8308_init(void) { pca9698_direction_output(0x20, 26, 1); diff --git a/board/hardkernel/odroid-c2/Kconfig b/board/hardkernel/odroid-c2/Kconfig new file mode 100644 index 0000000..687d9c6 --- /dev/null +++ b/board/hardkernel/odroid-c2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_C2 + +config SYS_BOARD + default "odroid-c2" + +config SYS_VENDOR + default "hardkernel" + +config SYS_CONFIG_NAME + default "odroid-c2" + +endif diff --git a/board/hardkernel/odroid-c2/MAINTAINERS b/board/hardkernel/odroid-c2/MAINTAINERS new file mode 100644 index 0000000..23ae1e7 --- /dev/null +++ b/board/hardkernel/odroid-c2/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID-C2 +M: Beniamino Galvani <b.galvani@gmail.com> +S: Maintained +F: board/hardkernel/odroid-c2/ +F: include/configs/odroid-c2.h +F: configs/odroid-c2_defconfig diff --git a/board/hardkernel/odroid-c2/Makefile b/board/hardkernel/odroid-c2/Makefile new file mode 100644 index 0000000..571044b --- /dev/null +++ b/board/hardkernel/odroid-c2/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := odroid-c2.o diff --git a/board/hardkernel/odroid-c2/README b/board/hardkernel/odroid-c2/README new file mode 100644 index 0000000..d6d266a --- /dev/null +++ b/board/hardkernel/odroid-c2/README @@ -0,0 +1,60 @@ +U-Boot for ODROID-C2 +==================== + +ODROID-C2 is a single board computer manufactured by Hardkernel +Co. Ltd with the following specifications: + + - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - Gigabit Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 2.0 Host, 1 x USB OTG + - eMMC, microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +Currently the u-boot port supports the following devices: + - serial + - Ethernet + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make odroid-c2_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > DIR=odroid-c2 + > git clone --depth 1 \ + https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \ + $DIR + > $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \ + --bl301 $DIR/fip/gxb/bl301.bin \ + --bl31 $DIR/fip/gxb/bl31.bin \ + --bl33 u-boot.bin \ + $DIR/fip.bin + > $DIR/fip/fip_create --dump $DIR/fip.bin + > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin + > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \ + --input $DIR/boot_new.bin \ + --output $DIR/u-boot.img + > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96 + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > BL1=$DIR/sd_fuse/bl1.bin.hardkernel + > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442 + > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1 + > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97 diff --git a/board/hardkernel/odroid-c2/odroid-c2.c b/board/hardkernel/odroid-c2/odroid-c2.c new file mode 100644 index 0000000..bd72100 --- /dev/null +++ b/board/hardkernel/odroid-c2/odroid-c2.c @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/gxbb.h> +#include <asm/arch/sm.h> +#include <dm/platdata.h> +#include <phy.h> + +#define EFUSE_SN_OFFSET 20 +#define EFUSE_SN_SIZE 16 +#define EFUSE_MAC_OFFSET 52 +#define EFUSE_MAC_SIZE 6 + +int board_init(void) +{ + return 0; +} + +static const struct eth_pdata gxbb_eth_pdata = { + .iobase = GXBB_ETH_BASE, + .phy_interface = PHY_INTERFACE_MODE_RGMII, +}; + +U_BOOT_DEVICE(meson_eth) = { + .name = "eth_designware", + .platdata = &gxbb_eth_pdata, +}; + +int misc_init_r(void) +{ + u8 mac_addr[EFUSE_MAC_SIZE]; + ssize_t len; + + /* Select Ethernet function */ + setbits_le32(GXBB_PINMUX(6), 0x3fff); + + /* Set RGMII mode */ + setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF | + GXBB_ETH_REG_0_TX_PHASE(1) | + GXBB_ETH_REG_0_TX_RATIO(4) | + GXBB_ETH_REG_0_PHY_CLK_EN | + GXBB_ETH_REG_0_CLK_EN); + + /* Enable power and clock gate */ + setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); + clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); + + /* Reset PHY on GPIOZ_14 */ + clrbits_le32(GXBB_GPIO_EN(3), BIT(14)); + clrbits_le32(GXBB_GPIO_OUT(3), BIT(14)); + mdelay(10); + setbits_le32(GXBB_GPIO_OUT(3), BIT(14)); + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, + mac_addr, EFUSE_MAC_SIZE); + if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + return 0; +} diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c index 72932ca..75bf1bb 100644 --- a/board/ifm/ac14xx/ac14xx.c +++ b/board/ifm/ac14xx/ac14xx.c @@ -607,11 +607,11 @@ int checkboard(void) return 0; } -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c index ca09767..4fc6809 100644 --- a/board/ifm/o2dnt2/o2dnt2.c +++ b/board/ifm/o2dnt2/o2dnt2.c @@ -303,7 +303,7 @@ void pci_init_board(void) } #endif -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) static void ft_adapt_flash_base(void *blob) { @@ -383,4 +383,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig index 4c06d0c..98eb4d1 100644 --- a/board/imgtec/malta/Kconfig +++ b/board/imgtec/malta/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "malta" +config SYS_TEXT_BASE + default 0xbe000000 if 32BIT + default 0xffffffffbe000000 if 64BIT + endif diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S index 534db1d..3d48cdc 100644 --- a/board/imgtec/malta/lowlevel_init.S +++ b/board/imgtec/malta/lowlevel_init.S @@ -10,6 +10,7 @@ #include <pci.h> #include <asm/addrspace.h> +#include <asm/asm.h> #include <asm/regdef.h> #include <asm/malta.h> #include <asm/mipsregs.h> @@ -34,7 +35,7 @@ lowlevel_init: mtc0 t0, CP0_CONFIG, 2 /* detect the core card */ - li t0, KSEG1ADDR(MALTA_REVISION) + PTR_LI t0, CKSEG1ADDR(MALTA_REVISION) lw t0, 0(t0) srl t0, t0, MALTA_REVISION_CORID_SHF andi t0, t0, (MALTA_REVISION_CORID_MSK >> \ @@ -68,12 +69,12 @@ lowlevel_init: */ _gt64120: /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - li t1, KSEG1ADDR(GT_DEF_BASE) + PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE) li t0, CPU_TO_GT32(0xdf000000) sw t0, GT_ISD_OFS(t1) /* setup MEM-to-PCI0 mapping */ - li t1, KSEG1ADDR(MALTA_GT_BASE) + PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE) /* setup PCI0 io window to 0x18000000-0x181fffff */ li t0, CPU_TO_GT32(0xc0000000) @@ -100,7 +101,7 @@ _gt64120: */ _msc01: /* setup peripheral bus controller clock divide */ - li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE) + PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE) li t1, 0x1 << MSC01_PBC_CLKCFG_SHF sw t1, MSC01_PBC_CLKCFG_OFS(t0) @@ -122,7 +123,7 @@ _msc01: sw t1, MSC01_PBC_CS0CFG_OFS(t0) /* setup basic address decode */ - li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE) + PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE) li t1, 0x0 li t2, -CONFIG_SYS_MEM_SIZE sw t1, MSC01_BIU_MCBAS1L_OFS(t0) @@ -157,7 +158,7 @@ _msc01: sw t2, MSC01_BIU_IP3MSK2L_OFS(t0) /* setup PCI memory */ - li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE) + PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE) li t1, MALTA_MSC01_PCIMEM_BASE li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK li t3, MALTA_MSC01_PCIMEM_MAP diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 3a9e780..4955043 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -12,7 +12,6 @@ #include <pci_gt64120.h> #include <pci_msc01.h> #include <rtc.h> -#include <serial.h> #include <asm/addrspace.h> #include <asm/io.h> @@ -161,18 +160,6 @@ int misc_init_r(void) return 0; } -struct serial_device *default_serial_console(void) -{ - switch (malta_sys_con()) { - case SYSCON_GT64120: - return &eserial1_device; - - default: - case SYSCON_MSC01: - return &eserial2_device; - } -} - void pci_init_board(void) { pci_dev_t bdf; diff --git a/board/intel/bayleybay/.gitignore b/board/intel/bayleybay/.gitignore new file mode 100644 index 0000000..6eb8a54 --- /dev/null +++ b/board/intel/bayleybay/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/board/intel/bayleybay/Makefile b/board/intel/bayleybay/Makefile index 88b5aad..52dda7d 100644 --- a/board/intel/bayleybay/Makefile +++ b/board/intel/bayleybay/Makefile @@ -5,3 +5,4 @@ # obj-y += bayleybay.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/intel/bayleybay/acpi/mainboard.asl b/board/intel/bayleybay/acpi/mainboard.asl new file mode 100644 index 0000000..21785ea --- /dev/null +++ b/board/intel/bayleybay/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/board/intel/bayleybay/dsdt.asl b/board/intel/bayleybay/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/intel/bayleybay/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/intel/galileo/.gitignore b/board/intel/galileo/.gitignore new file mode 100644 index 0000000..6eb8a54 --- /dev/null +++ b/board/intel/galileo/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig index 6515bac..87a0ec4 100644 --- a/board/intel/galileo/Kconfig +++ b/board/intel/galileo/Kconfig @@ -21,4 +21,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_QUARK select BOARD_ROMSIZE_KB_1024 +config SMBIOS_PRODUCT_NAME + default "GalileoGen2" + help + Override the default product name U-Boot reports in the SMBIOS + table, to be compatible with the Intel provided UEFI BIOS, as + Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and + drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of + it to do different board level configuration. + + This can be "Galileo" for GEN1 Galileo board. + endif diff --git a/board/intel/galileo/Makefile b/board/intel/galileo/Makefile index 8356df1..bbe2f8b 100644 --- a/board/intel/galileo/Makefile +++ b/board/intel/galileo/Makefile @@ -5,3 +5,4 @@ # obj-y += galileo.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/intel/galileo/acpi/mainboard.asl b/board/intel/galileo/acpi/mainboard.asl new file mode 100644 index 0000000..21785ea --- /dev/null +++ b/board/intel/galileo/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/board/intel/galileo/dsdt.asl b/board/intel/galileo/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/intel/galileo/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/intel/minnowmax/.gitignore b/board/intel/minnowmax/.gitignore new file mode 100644 index 0000000..6eb8a54 --- /dev/null +++ b/board/intel/minnowmax/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile index 1a61432..73e5a8f 100644 --- a/board/intel/minnowmax/Makefile +++ b/board/intel/minnowmax/Makefile @@ -5,3 +5,4 @@ # obj-y += minnowmax.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/intel/minnowmax/acpi/mainboard.asl b/board/intel/minnowmax/acpi/mainboard.asl new file mode 100644 index 0000000..21785ea --- /dev/null +++ b/board/intel/minnowmax/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/board/intel/minnowmax/dsdt.asl b/board/intel/minnowmax/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/intel/minnowmax/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c index 4ab7160..2e52d51 100644 --- a/board/intercontrol/digsy_mtc/digsy_mtc.c +++ b/board/intercontrol/digsy_mtc/digsy_mtc.c @@ -378,7 +378,7 @@ void ide_set_reset(int idereset) #endif /* CONFIG_IDE_RESET */ #endif /* CONFIG_CMD_IDE */ -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP static void ft_delete_node(void *fdt, const char *compat) { int off = -1; @@ -481,4 +481,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c index 2078f53..2e62355 100644 --- a/board/ipek01/ipek01.c +++ b/board/ipek01/ipek01.c @@ -195,7 +195,7 @@ void pci_init_board (void) } #endif -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup (blob, bd); @@ -203,7 +203,7 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ int board_eth_init(bd_t *bis) { diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index 8856393..d56902b 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -282,11 +282,11 @@ void ide_set_reset (int idereset) } #endif -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); return 0; } -#endif +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/microchip/pic32mzda/Kconfig b/board/microchip/pic32mzda/Kconfig index 8acb393..4f08e98 100644 --- a/board/microchip/pic32mzda/Kconfig +++ b/board/microchip/pic32mzda/Kconfig @@ -10,4 +10,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "pic32mzdask" +config SYS_TEXT_BASE + default 0x9d004000 + endif diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig index c518079..df7c029 100644 --- a/board/micronas/vct/Kconfig +++ b/board/micronas/vct/Kconfig @@ -9,6 +9,21 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "vct" +config SYS_TEXT_BASE + default 0x87000000 + +config SYS_DCACHE_SIZE + default 16384 + +config SYS_DCACHE_LINE_SIZE + default 32 + +config SYS_ICACHE_SIZE + default 16384 + +config SYS_ICACHE_LINE_SIZE + default 32 + menu "vct board options" choice diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index 4d0ebaa..dc237c1 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -184,14 +184,14 @@ int checkboard(void) } -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ #if defined(CONFIG_STATUS_LED) diff --git a/board/munices/munices.c b/board/munices/munices.c index 23d0f56..8f292ea 100644 --- a/board/munices/munices.c +++ b/board/munices/munices.c @@ -145,11 +145,11 @@ void pci_init_board(void) } #endif -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); return 0; } -#endif +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index ba15e2e..f04f843 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -110,11 +110,11 @@ int tegra_pcie_board_init(void) } /* GPIO: PEX = 3.3V */ - err = gpio_request(GPIO_PL7, "PEX"); + err = gpio_request(TEGRA_GPIO(L, 7), "PEX"); if (err < 0) return err; - gpio_direction_output(GPIO_PL7, 1); + gpio_direction_output(TEGRA_GPIO(L, 7), 1); /* TPS659110: LDO2_REG = 1.05V, ACTIVE */ data[0] = 0x15; diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h index 7eb1e6c..7955ca5 100644 --- a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h +++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h @@ -15,71 +15,71 @@ #ifndef _PINMUX_CONFIG_E2220_1170_H_ #define _PINMUX_CONFIG_E2220_1170_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config e2220_1170_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A5, IN), - GPIO_INIT(A6, IN), - GPIO_INIT(B4, IN), - GPIO_INIT(E6, IN), - GPIO_INIT(G2, OUT0), - GPIO_INIT(G3, OUT0), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H1, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(H6, OUT0), - GPIO_INIT(H7, OUT0), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I3, OUT0), - GPIO_INIT(K0, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, OUT0), - GPIO_INIT(K3, OUT0), - GPIO_INIT(K4, IN), - GPIO_INIT(K5, OUT0), - GPIO_INIT(K6, IN), - GPIO_INIT(K7, OUT0), - GPIO_INIT(L0, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, OUT0), - GPIO_INIT(S6, OUT0), - GPIO_INIT(S7, OUT0), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V2, OUT0), - GPIO_INIT(V3, IN), - GPIO_INIT(V5, OUT0), - GPIO_INIT(V6, OUT0), - GPIO_INIT(X0, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X2, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y0, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z4, OUT0), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(BB3, OUT0), - GPIO_INIT(BB4, IN), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC5, OUT0), - GPIO_INIT(CC6, IN), - GPIO_INIT(CC7, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 5, IN), + GPIO_INIT(A, 6, IN), + GPIO_INIT(B, 4, IN), + GPIO_INIT(E, 6, IN), + GPIO_INIT(G, 2, OUT0), + GPIO_INIT(G, 3, OUT0), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 1, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(H, 6, OUT0), + GPIO_INIT(H, 7, OUT0), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(I, 3, OUT0), + GPIO_INIT(K, 0, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, OUT0), + GPIO_INIT(K, 3, OUT0), + GPIO_INIT(K, 4, IN), + GPIO_INIT(K, 5, OUT0), + GPIO_INIT(K, 6, IN), + GPIO_INIT(K, 7, OUT0), + GPIO_INIT(L, 0, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 5, OUT0), + GPIO_INIT(S, 6, OUT0), + GPIO_INIT(S, 7, OUT0), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, OUT0), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 2, OUT0), + GPIO_INIT(V, 3, IN), + GPIO_INIT(V, 5, OUT0), + GPIO_INIT(V, 6, OUT0), + GPIO_INIT(X, 0, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 2, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 5, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 0, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 4, OUT0), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(BB, 3, OUT0), + GPIO_INIT(BB, 4, IN), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 5, OUT0), + GPIO_INIT(CC, 6, IN), + GPIO_INIT(CC, 7, OUT0), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h index 00e0cdc..01237db 100644 --- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -15,63 +15,63 @@ #ifndef _PINMUX_CONFIG_JETSON_TK1_H_ #define _PINMUX_CONFIG_JETSON_TK1_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(G0, IN), - GPIO_INIT(G1, IN), - GPIO_INIT(G2, IN), - GPIO_INIT(G3, IN), - GPIO_INIT(G4, IN), - GPIO_INIT(H2, OUT0), - GPIO_INIT(H4, IN), - GPIO_INIT(H7, IN), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I6, IN), - GPIO_INIT(J0, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, IN), - GPIO_INIT(K4, OUT0), - GPIO_INIT(K6, OUT0), - GPIO_INIT(N7, IN), - GPIO_INIT(O1, IN), - GPIO_INIT(O4, IN), - GPIO_INIT(P2, OUT0), - GPIO_INIT(Q0, IN), - GPIO_INIT(Q3, IN), - GPIO_INIT(Q5, IN), - GPIO_INIT(R0, OUT0), - GPIO_INIT(R2, OUT0), - GPIO_INIT(R4, IN), - GPIO_INIT(R7, IN), - GPIO_INIT(S7, IN), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, IN), - GPIO_INIT(U0, IN), - GPIO_INIT(U1, IN), - GPIO_INIT(U2, IN), - GPIO_INIT(U3, IN), - GPIO_INIT(U4, IN), - GPIO_INIT(U5, IN), - GPIO_INIT(U6, IN), - GPIO_INIT(V0, IN), - GPIO_INIT(V1, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X7, OUT0), - GPIO_INIT(BB3, OUT0), - GPIO_INIT(BB5, OUT0), - GPIO_INIT(BB6, OUT0), - GPIO_INIT(BB7, OUT0), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC2, IN), - GPIO_INIT(EE2, OUT1), + /* port, pin, init_val */ + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 1, IN), + GPIO_INIT(G, 2, IN), + GPIO_INIT(G, 3, IN), + GPIO_INIT(G, 4, IN), + GPIO_INIT(H, 2, OUT0), + GPIO_INIT(H, 4, IN), + GPIO_INIT(H, 7, IN), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 6, IN), + GPIO_INIT(J, 0, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, IN), + GPIO_INIT(K, 4, OUT0), + GPIO_INIT(K, 6, OUT0), + GPIO_INIT(N, 7, IN), + GPIO_INIT(O, 1, IN), + GPIO_INIT(O, 4, IN), + GPIO_INIT(P, 2, OUT0), + GPIO_INIT(Q, 0, IN), + GPIO_INIT(Q, 3, IN), + GPIO_INIT(Q, 5, IN), + GPIO_INIT(R, 0, OUT0), + GPIO_INIT(R, 2, OUT0), + GPIO_INIT(R, 4, IN), + GPIO_INIT(R, 7, IN), + GPIO_INIT(S, 7, IN), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, IN), + GPIO_INIT(U, 0, IN), + GPIO_INIT(U, 1, IN), + GPIO_INIT(U, 2, IN), + GPIO_INIT(U, 3, IN), + GPIO_INIT(U, 4, IN), + GPIO_INIT(U, 5, IN), + GPIO_INIT(U, 6, IN), + GPIO_INIT(V, 0, IN), + GPIO_INIT(V, 1, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 7, OUT0), + GPIO_INIT(BB, 3, OUT0), + GPIO_INIT(BB, 5, OUT0), + GPIO_INIT(BB, 6, OUT0), + GPIO_INIT(BB, 7, OUT0), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 2, IN), + GPIO_INIT(EE, 2, OUT1), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index ba96401..8f68ae9 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -36,8 +36,9 @@ void pinmux_init(void) int tegra_board_id(void) { - static const int vector[] = {GPIO_PQ3, GPIO_PT1, GPIO_PX1, - GPIO_PX4, -1}; + static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1), + TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4), + -1}; gpio_claim_vector(vector, "board_id%d"); return gpio_get_values_as_int(vector); diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h index dca0171..fd7f1d1 100644 --- a/board/nvidia/nyan-big/pinmux-config-nyan-big.h +++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h @@ -15,59 +15,59 @@ #ifndef _PINMUX_CONFIG_NYAN_BIG_H_ #define _PINMUX_CONFIG_NYAN_BIG_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config nyan_big_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A0, IN), - GPIO_INIT(C7, IN), - GPIO_INIT(G0, IN), - GPIO_INIT(G1, IN), - GPIO_INIT(G2, IN), - GPIO_INIT(G3, IN), - GPIO_INIT(H2, IN), - GPIO_INIT(H4, IN), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, OUT1), - GPIO_INIT(I0, IN), - GPIO_INIT(I1, IN), - GPIO_INIT(I5, OUT1), - GPIO_INIT(I6, IN), - GPIO_INIT(I7, IN), - GPIO_INIT(J0, IN), - GPIO_INIT(J7, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, IN), - GPIO_INIT(K4, OUT0), - GPIO_INIT(K6, OUT0), - GPIO_INIT(K7, IN), - GPIO_INIT(N7, IN), - GPIO_INIT(P2, OUT0), - GPIO_INIT(Q0, IN), - GPIO_INIT(Q2, IN), - GPIO_INIT(Q3, IN), - GPIO_INIT(Q6, IN), - GPIO_INIT(Q7, IN), - GPIO_INIT(R0, OUT0), - GPIO_INIT(R1, IN), - GPIO_INIT(R4, IN), - GPIO_INIT(R7, IN), - GPIO_INIT(S3, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S7, IN), - GPIO_INIT(T1, IN), - GPIO_INIT(U4, IN), - GPIO_INIT(U5, IN), - GPIO_INIT(U6, IN), - GPIO_INIT(V0, IN), - GPIO_INIT(W3, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X7, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 0, IN), + GPIO_INIT(C, 7, IN), + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 1, IN), + GPIO_INIT(G, 2, IN), + GPIO_INIT(G, 3, IN), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 4, IN), + GPIO_INIT(H, 6, IN), + GPIO_INIT(H, 7, OUT1), + GPIO_INIT(I, 0, IN), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 5, OUT1), + GPIO_INIT(I, 6, IN), + GPIO_INIT(I, 7, IN), + GPIO_INIT(J, 0, IN), + GPIO_INIT(J, 7, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, IN), + GPIO_INIT(K, 4, OUT0), + GPIO_INIT(K, 6, OUT0), + GPIO_INIT(K, 7, IN), + GPIO_INIT(N, 7, IN), + GPIO_INIT(P, 2, OUT0), + GPIO_INIT(Q, 0, IN), + GPIO_INIT(Q, 2, IN), + GPIO_INIT(Q, 3, IN), + GPIO_INIT(Q, 6, IN), + GPIO_INIT(Q, 7, IN), + GPIO_INIT(R, 0, OUT0), + GPIO_INIT(R, 1, IN), + GPIO_INIT(R, 4, IN), + GPIO_INIT(R, 7, IN), + GPIO_INIT(S, 3, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 7, IN), + GPIO_INIT(T, 1, IN), + GPIO_INIT(U, 4, IN), + GPIO_INIT(U, 5, IN), + GPIO_INIT(U, 6, IN), + GPIO_INIT(V, 0, IN), + GPIO_INIT(W, 3, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 7, OUT0), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h index 35706b4..24acbcc 100644 --- a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h +++ b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h @@ -15,62 +15,62 @@ #ifndef _PINMUX_CONFIG_P2371_0000_H_ #define _PINMUX_CONFIG_P2371_0000_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config p2371_0000_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A5, IN), - GPIO_INIT(E4, OUT0), - GPIO_INIT(E6, IN), - GPIO_INIT(G0, IN), - GPIO_INIT(G3, OUT0), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(H6, OUT0), - GPIO_INIT(H7, OUT0), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I3, OUT0), - GPIO_INIT(K4, IN), - GPIO_INIT(K5, OUT0), - GPIO_INIT(K6, IN), - GPIO_INIT(K7, OUT0), - GPIO_INIT(L0, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, OUT0), - GPIO_INIT(S6, OUT0), - GPIO_INIT(S7, OUT0), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V2, OUT0), - GPIO_INIT(V5, OUT0), - GPIO_INIT(V6, OUT0), - GPIO_INIT(V7, OUT1), - GPIO_INIT(X0, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X2, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z4, OUT0), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(BB3, OUT0), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC6, IN), - GPIO_INIT(CC7, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 5, IN), + GPIO_INIT(E, 4, OUT0), + GPIO_INIT(E, 6, IN), + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 3, OUT0), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(H, 6, OUT0), + GPIO_INIT(H, 7, OUT0), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(I, 3, OUT0), + GPIO_INIT(K, 4, IN), + GPIO_INIT(K, 5, OUT0), + GPIO_INIT(K, 6, IN), + GPIO_INIT(K, 7, OUT0), + GPIO_INIT(L, 0, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 5, OUT0), + GPIO_INIT(S, 6, OUT0), + GPIO_INIT(S, 7, OUT0), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, OUT0), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 2, OUT0), + GPIO_INIT(V, 5, OUT0), + GPIO_INIT(V, 6, OUT0), + GPIO_INIT(V, 7, OUT1), + GPIO_INIT(X, 0, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 2, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 5, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 4, OUT0), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(BB, 3, OUT0), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 6, IN), + GPIO_INIT(CC, 7, OUT0), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h index d5be6ec..601728e 100644 --- a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h +++ b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h @@ -15,73 +15,73 @@ #ifndef _PINMUX_CONFIG_P2371_2180_H_ #define _PINMUX_CONFIG_P2371_2180_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config p2371_2180_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A5, IN), - GPIO_INIT(B0, IN), - GPIO_INIT(B1, IN), - GPIO_INIT(B2, IN), - GPIO_INIT(B3, IN), - GPIO_INIT(C0, IN), - GPIO_INIT(C1, IN), - GPIO_INIT(C2, IN), - GPIO_INIT(C3, IN), - GPIO_INIT(C4, IN), - GPIO_INIT(E4, IN), - GPIO_INIT(E5, IN), - GPIO_INIT(E6, IN), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H1, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, IN), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(K4, IN), - GPIO_INIT(K5, OUT0), - GPIO_INIT(K6, IN), - GPIO_INIT(K7, IN), - GPIO_INIT(L1, IN), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, OUT0), - GPIO_INIT(S6, OUT0), - GPIO_INIT(S7, OUT0), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(U2, IN), - GPIO_INIT(U3, IN), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V2, OUT0), - GPIO_INIT(V3, IN), - GPIO_INIT(V5, OUT0), - GPIO_INIT(V6, OUT0), - GPIO_INIT(X0, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X2, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y0, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z2, IN), - GPIO_INIT(Z3, OUT0), - GPIO_INIT(BB0, IN), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(BB3, IN), - GPIO_INIT(CC1, IN), + /* port, pin, init_val */ + GPIO_INIT(A, 5, IN), + GPIO_INIT(B, 0, IN), + GPIO_INIT(B, 1, IN), + GPIO_INIT(B, 2, IN), + GPIO_INIT(B, 3, IN), + GPIO_INIT(C, 0, IN), + GPIO_INIT(C, 1, IN), + GPIO_INIT(C, 2, IN), + GPIO_INIT(C, 3, IN), + GPIO_INIT(C, 4, IN), + GPIO_INIT(E, 4, IN), + GPIO_INIT(E, 5, IN), + GPIO_INIT(E, 6, IN), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 1, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(H, 6, IN), + GPIO_INIT(H, 7, IN), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(K, 4, IN), + GPIO_INIT(K, 5, OUT0), + GPIO_INIT(K, 6, IN), + GPIO_INIT(K, 7, IN), + GPIO_INIT(L, 1, IN), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 5, OUT0), + GPIO_INIT(S, 6, OUT0), + GPIO_INIT(S, 7, OUT0), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, OUT0), + GPIO_INIT(U, 2, IN), + GPIO_INIT(U, 3, IN), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 2, OUT0), + GPIO_INIT(V, 3, IN), + GPIO_INIT(V, 5, OUT0), + GPIO_INIT(V, 6, OUT0), + GPIO_INIT(X, 0, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 2, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 5, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 0, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 2, IN), + GPIO_INIT(Z, 3, OUT0), + GPIO_INIT(BB, 0, IN), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(BB, 3, IN), + GPIO_INIT(CC, 1, IN), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index d80a7d0..7ce656f 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -58,6 +58,6 @@ void pinmux_init(void) void start_cpu_fan(void) { /* GPIO_PE4 is PS_VDD_FAN_ENABLE */ - gpio_request(GPIO_PE4, "FAN_VDD"); - gpio_direction_output(GPIO_PE4, 1); + gpio_request(TEGRA_GPIO(E, 4), "FAN_VDD"); + gpio_direction_output(TEGRA_GPIO(E, 4), 1); } diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h index d323301..dd4228f 100644 --- a/board/nvidia/p2571/pinmux-config-p2571.h +++ b/board/nvidia/p2571/pinmux-config-p2571.h @@ -15,37 +15,37 @@ #ifndef _PINMUX_CONFIG_P2571_H_ #define _PINMUX_CONFIG_P2571_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config p2571_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A0, IN), - GPIO_INIT(A5, IN), - GPIO_INIT(D4, IN), - GPIO_INIT(E4, OUT0), - GPIO_INIT(G0, IN), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V6, OUT1), - GPIO_INIT(X4, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z4, OUT0), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC3, IN), + /* port, pin, init_val */ + GPIO_INIT(A, 0, IN), + GPIO_INIT(A, 5, IN), + GPIO_INIT(D, 4, IN), + GPIO_INIT(E, 4, OUT0), + GPIO_INIT(G, 0, IN), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 6, OUT1), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 4, OUT0), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 3, IN), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig new file mode 100644 index 0000000..1b1116f --- /dev/null +++ b/board/nvidia/p2771-0000/Kconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +if TARGET_P2771_0000 + +config SYS_BOARD + default "p2771-0000" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "p2771-0000" + +endif diff --git a/board/nvidia/p2771-0000/MAINTAINERS b/board/nvidia/p2771-0000/MAINTAINERS new file mode 100644 index 0000000..4fc4ebd --- /dev/null +++ b/board/nvidia/p2771-0000/MAINTAINERS @@ -0,0 +1,6 @@ +P2771-0000 BOARD +M: Stephen Warren <swarren@nvidia.com> +S: Maintained +F: board/nvidia/p2771-0000/ +F: include/configs/p2771-0000.h +F: configs/p2771-0000_defconfig diff --git a/board/nvidia/p2771-0000/Makefile b/board/nvidia/p2771-0000/Makefile new file mode 100644 index 0000000..b28a47d --- /dev/null +++ b/board/nvidia/p2771-0000/Makefile @@ -0,0 +1,5 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +obj-y += p2771-0000.o diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c new file mode 100644 index 0000000..4ba8ebc --- /dev/null +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 2d07001..fc9c1c9 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -20,8 +20,8 @@ void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ - gpio_request(GPIO_PI3, "uart_en"); - gpio_direction_output(GPIO_PI3, 0); + gpio_request(TEGRA_GPIO(I, 3), "uart_en"); + gpio_direction_output(TEGRA_GPIO(I, 3), 0); } #endif diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h index fb444b3..59d53ef 100644 --- a/board/nvidia/venice2/pinmux-config-venice2.h +++ b/board/nvidia/venice2/pinmux-config-venice2.h @@ -15,70 +15,70 @@ #ifndef _PINMUX_CONFIG_VENICE2_H_ #define _PINMUX_CONFIG_VENICE2_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config venice2_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A0, IN), - GPIO_INIT(C7, IN), - GPIO_INIT(G0, IN), - GPIO_INIT(G1, IN), - GPIO_INIT(G2, IN), - GPIO_INIT(G3, IN), - GPIO_INIT(H2, IN), - GPIO_INIT(H4, IN), - GPIO_INIT(H5, OUT0), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, OUT1), - GPIO_INIT(I0, IN), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I4, OUT0), - GPIO_INIT(I5, OUT1), - GPIO_INIT(I6, IN), - GPIO_INIT(J0, IN), - GPIO_INIT(J7, IN), - GPIO_INIT(K0, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, IN), - GPIO_INIT(K3, IN), - GPIO_INIT(K4, OUT0), - GPIO_INIT(K6, OUT0), - GPIO_INIT(K7, IN), - GPIO_INIT(N7, IN), - GPIO_INIT(O2, IN), - GPIO_INIT(O5, IN), - GPIO_INIT(O6, OUT0), - GPIO_INIT(O7, IN), - GPIO_INIT(P2, OUT0), - GPIO_INIT(Q0, IN), - GPIO_INIT(Q2, IN), - GPIO_INIT(Q3, IN), - GPIO_INIT(Q6, IN), - GPIO_INIT(Q7, IN), - GPIO_INIT(R0, OUT0), - GPIO_INIT(R1, IN), - GPIO_INIT(R4, IN), - GPIO_INIT(S0, IN), - GPIO_INIT(S3, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S7, IN), - GPIO_INIT(T1, IN), - GPIO_INIT(U4, IN), - GPIO_INIT(U5, IN), - GPIO_INIT(U6, IN), - GPIO_INIT(V0, IN), - GPIO_INIT(V1, IN), - GPIO_INIT(W3, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X7, OUT0), - GPIO_INIT(CC5, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 0, IN), + GPIO_INIT(C, 7, IN), + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 1, IN), + GPIO_INIT(G, 2, IN), + GPIO_INIT(G, 3, IN), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 4, IN), + GPIO_INIT(H, 5, OUT0), + GPIO_INIT(H, 6, IN), + GPIO_INIT(H, 7, OUT1), + GPIO_INIT(I, 0, IN), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(I, 4, OUT0), + GPIO_INIT(I, 5, OUT1), + GPIO_INIT(I, 6, IN), + GPIO_INIT(J, 0, IN), + GPIO_INIT(J, 7, IN), + GPIO_INIT(K, 0, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, IN), + GPIO_INIT(K, 3, IN), + GPIO_INIT(K, 4, OUT0), + GPIO_INIT(K, 6, OUT0), + GPIO_INIT(K, 7, IN), + GPIO_INIT(N, 7, IN), + GPIO_INIT(O, 2, IN), + GPIO_INIT(O, 5, IN), + GPIO_INIT(O, 6, OUT0), + GPIO_INIT(O, 7, IN), + GPIO_INIT(P, 2, OUT0), + GPIO_INIT(Q, 0, IN), + GPIO_INIT(Q, 2, IN), + GPIO_INIT(Q, 3, IN), + GPIO_INIT(Q, 6, IN), + GPIO_INIT(Q, 7, IN), + GPIO_INIT(R, 0, OUT0), + GPIO_INIT(R, 1, IN), + GPIO_INIT(R, 4, IN), + GPIO_INIT(S, 0, IN), + GPIO_INIT(S, 3, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 7, IN), + GPIO_INIT(T, 1, IN), + GPIO_INIT(U, 4, IN), + GPIO_INIT(U, 5, IN), + GPIO_INIT(U, 6, IN), + GPIO_INIT(V, 0, IN), + GPIO_INIT(V, 1, IN), + GPIO_INIT(W, 3, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 7, OUT0), + GPIO_INIT(CC, 5, OUT0), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig index 251db6a..ef8905d 100644 --- a/board/pb1x00/Kconfig +++ b/board/pb1x00/Kconfig @@ -9,4 +9,19 @@ config SYS_SOC config SYS_CONFIG_NAME default "pb1x00" +config SYS_TEXT_BASE + default 0x83800000 + +config SYS_DCACHE_SIZE + default 16384 + +config SYS_DCACHE_LINE_SIZE + default 32 + +config SYS_ICACHE_SIZE + default 16384 + +config SYS_ICACHE_LINE_SIZE + default 32 + endif diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c index 81f3024..d91d427 100644 --- a/board/pdm360ng/pdm360ng.c +++ b/board/pdm360ng/pdm360ng.c @@ -429,7 +429,7 @@ int checkboard (void) return 0; } -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP #ifdef CONFIG_FDT_FIXUP_PARTITIONS struct node_info nodes[] = { { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, }, @@ -529,7 +529,7 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ /* * If argument is NULL, set the LCD brightness to the diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c index ed41de1..8a9de0d 100644 --- a/board/phytec/pcm030/pcm030.c +++ b/board/phytec/pcm030/pcm030.c @@ -163,14 +163,14 @@ void pci_init_board(void) } #endif -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig index f7e768a..4fd6a71 100644 --- a/board/qca/ap121/Kconfig +++ b/board/qca/ap121/Kconfig @@ -9,4 +9,19 @@ config SYS_BOARD config SYS_CONFIG_NAME default "ap121" +config SYS_TEXT_BASE + default 0x9f000000 + +config SYS_DCACHE_SIZE + default 32768 + +config SYS_DCACHE_LINE_SIZE + default 32 + +config SYS_ICACHE_SIZE + default 65536 + +config SYS_ICACHE_LINE_SIZE + default 32 + endif diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c index d6c60fe..e245faa 100644 --- a/board/qca/ap121/ap121.c +++ b/board/qca/ap121/ap121.c @@ -10,6 +10,7 @@ #include <asm/types.h> #include <mach/ar71xx_regs.h> #include <mach/ddr.h> +#include <mach/ath79.h> #include <debug_uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -46,5 +47,6 @@ int board_early_init_f(void) debug_uart_init(); #endif ddr_init(); + ath79_eth_reset(); return 0; } diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig index 4cdac0d..74c632a 100644 --- a/board/qca/ap143/Kconfig +++ b/board/qca/ap143/Kconfig @@ -9,4 +9,19 @@ config SYS_BOARD config SYS_CONFIG_NAME default "ap143" +config SYS_TEXT_BASE + default 0x9f000000 + +config SYS_DCACHE_SIZE + default 32768 + +config SYS_DCACHE_LINE_SIZE + default 32 + +config SYS_ICACHE_SIZE + default 65536 + +config SYS_ICACHE_LINE_SIZE + default 32 + endif diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c index 1572472..e921ea5 100644 --- a/board/qca/ap143/ap143.c +++ b/board/qca/ap143/ap143.c @@ -10,6 +10,7 @@ #include <asm/types.h> #include <mach/ar71xx_regs.h> #include <mach/ddr.h> +#include <mach/ath79.h> #include <debug_uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -62,5 +63,6 @@ int board_early_init_f(void) debug_uart_init(); #endif ddr_init(); + ath79_eth_reset(); return 0; } diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig index 18d78b5..e696a12 100644 --- a/board/qemu-mips/Kconfig +++ b/board/qemu-mips/Kconfig @@ -7,4 +7,20 @@ config SYS_CONFIG_NAME default "qemu-mips" if 32BIT default "qemu-mips64" if 64BIT +config SYS_TEXT_BASE + default 0xbfc00000 if 32BIT + default 0xffffffffbfc00000 if 64BIT + +config SYS_DCACHE_SIZE + default 16384 + +config SYS_DCACHE_LINE_SIZE + default 32 + +config SYS_ICACHE_SIZE + default 16384 + +config SYS_ICACHE_LINE_SIZE + default 32 + endif diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds index 053df64..6cd4056 100644 --- a/board/renesas/sh7752evb/u-boot.lds +++ b/board/renesas/sh7752evb/u-boot.lds @@ -65,6 +65,7 @@ SECTIONS KEEP(*(SORT(.u_boot_list*))); } + PROVIDE (__init_end = .); PROVIDE (reloc_dst_end = .); /* _reloc_dst_end = .; */ diff --git a/board/renesas/sh7753evb/u-boot.lds b/board/renesas/sh7753evb/u-boot.lds index 053df64..6cd4056 100644 --- a/board/renesas/sh7753evb/u-boot.lds +++ b/board/renesas/sh7753evb/u-boot.lds @@ -65,6 +65,7 @@ SECTIONS KEEP(*(SORT(.u_boot_list*))); } + PROVIDE (__init_end = .); PROVIDE (reloc_dst_end = .); /* _reloc_dst_end = .; */ diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds index 4027fe3..d701367 100644 --- a/board/renesas/sh7757lcr/u-boot.lds +++ b/board/renesas/sh7757lcr/u-boot.lds @@ -66,6 +66,7 @@ SECTIONS KEEP(*(SORT(.u_boot_list*))); } + PROVIDE (__init_end = .); PROVIDE (reloc_dst_end = .); /* _reloc_dst_end = .; */ diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 3cc01cb..e2cb94e 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -194,7 +194,7 @@ void lcd_show_board_info(void) nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; flash_size = 0; for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 276ff80..e9f9b67 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -293,7 +293,7 @@ void lcd_show_board_info(void) nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; flash_size = 0; for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 1334c22..0eb066c 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -27,6 +27,8 @@ #include <usb.h> #include <dwc3-uboot.h> #include <samsung/misc.h> +#include <dm/pinctrl.h> +#include <dm.h> DECLARE_GLOBAL_DATA_PTR; @@ -97,7 +99,7 @@ int board_init(void) int dram_init(void) { unsigned int i; - u32 addr; + unsigned long addr; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); @@ -109,7 +111,7 @@ int dram_init(void) void dram_init_banksize(void) { unsigned int i; - u32 addr, size; + unsigned long addr, size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); @@ -122,6 +124,7 @@ void dram_init_banksize(void) static int board_uart_init(void) { +#ifndef CONFIG_PINCTRL_EXYNOS int err, uart_id, ret = 0; for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { @@ -133,6 +136,9 @@ static int board_uart_init(void) } } return ret; +#else + return 0; +#endif } #ifdef CONFIG_BOARD_EARLY_INIT_F @@ -152,21 +158,6 @@ int board_early_init_f(void) board_i2c_init(gd->fdt_blob); #endif -#if defined(CONFIG_EXYNOS_FB) - /* - * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs - * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, - * to reserve frame-buffer memory at a very early stage. So, we need - * to fill panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix - * before lcd_setmem() is called. - */ - err = exynos_lcd_early_init(gd->fdt_blob); - if (err) { - debug("LCD early init failed\n"); - return err; - } -#endif - return exynos_early_init_f(); } #endif diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index 4d9e151..2e3b16d 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -147,164 +147,6 @@ int board_get_revision(void) return 0; } -#ifdef CONFIG_LCD - -static int board_dp_bridge_init(struct udevice *dev) -{ - const int max_tries = 10; - int num_tries; - int ret; - - debug("%s\n", __func__); - ret = video_bridge_attach(dev); - if (ret) { - debug("video bridge init failed: %d\n", ret); - return ret; - } - - /* - * We need to wait for 90ms after bringing up the bridge since there - * is a phantom "high" on the HPD chip during its bootup. The phantom - * high comes within 7ms of de-asserting PD and persists for at least - * 15ms. The real high comes roughly 50ms after PD is de-asserted. The - * phantom high makes it hard for us to know when the NXP chip is up. - */ - mdelay(90); - - for (num_tries = 0; num_tries < max_tries; num_tries++) { - /* Check HPD. If it's high, or we don't have it, all is well */ - ret = video_bridge_check_attached(dev); - if (!ret || ret == -ENOENT) - return 0; - - debug("%s: eDP bridge failed to come up; try %d of %d\n", - __func__, num_tries, max_tries); - } - - /* Immediately go into bridge reset if the hp line is not high */ - return -EIO; -} - -static int board_dp_bridge_setup(const void *blob) -{ - const int max_tries = 2; - int num_tries; - struct udevice *dev; - int ret; - - /* Configure I2C registers for Parade bridge */ - ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev); - if (ret) { - debug("video bridge init failed: %d\n", ret); - return ret; - } - - if (strncmp(dev->driver->name, "parade", 6)) { - /* Mux HPHPD to the special hotplug detect mode */ - exynos_pinmux_config(PERIPH_ID_DPHPD, 0); - } - - for (num_tries = 0; num_tries < max_tries; num_tries++) { - ret = board_dp_bridge_init(dev); - if (!ret) - return 0; - if (num_tries == max_tries - 1) - break; - - /* - * If we're here, the bridge chip failed to initialise. - * Power down the bridge in an attempt to reset. - */ - video_bridge_set_active(dev, false); - - /* - * Arbitrarily wait 300ms here with DP_N low. Don't know for - * sure how long we should wait, but we're being paranoid. - */ - mdelay(300); - } - - return ret; -} - -void exynos_cfg_lcd_gpio(void) -{ - /* For Backlight */ - gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight"); - gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT); - gpio_set_value(EXYNOS5_GPIO_B20, 1); -} - -void exynos_set_dp_phy(unsigned int onoff) -{ - set_dp_phy_ctrl(onoff); -} - -static int board_dp_set_backlight(int percent) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev); - if (!ret) - ret = video_bridge_set_backlight(dev, percent); - - return ret; -} - -void exynos_backlight_on(unsigned int on) -{ - struct udevice *dev; - int ret; - - debug("%s(%u)\n", __func__, on); - if (!on) - return; - - ret = regulator_get_by_platname("vcd_led", &dev); - if (!ret) - ret = regulator_set_enable(dev, true); - if (ret) - debug("Failed to enable backlight: ret=%d\n", ret); - - /* T5 in the LCD timing spec (defined as > 10ms) */ - mdelay(10); - - /* board_dp_backlight_pwm */ - gpio_direction_output(EXYNOS5_GPIO_B20, 1); - - /* T6 in the LCD timing spec (defined as > 10ms) */ - mdelay(10); - - /* try to set the backlight in the bridge registers */ - ret = board_dp_set_backlight(80); - - /* if we have no bridge or it does not support backlight, use a GPIO */ - if (ret == -ENODEV || ret == -ENOSYS) { - gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en"); - gpio_direction_output(EXYNOS5_GPIO_X30, 1); - } -} - -void exynos_lcd_power_on(void) -{ - struct udevice *dev; - int ret; - - debug("%s\n", __func__); - ret = regulator_get_by_platname("lcd_vdd", &dev); - if (!ret) - ret = regulator_set_enable(dev, true); - if (ret) - debug("Failed to enable LCD panel: ret=%d\n", ret); - - ret = board_dp_bridge_setup(gd->fdt_blob); - if (ret && ret != -ENODEV) - printf("LCD bridge failed to enable: %d\n", ret); -} - -#endif - #ifdef CONFIG_USB_DWC3 static struct dwc3_device dwc3_device_data = { .maximum_speed = USB_SPEED_SUPER, diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index da0d4db..77d0a4e 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -147,6 +147,7 @@ static int key_pressed(int key) return value; } +#ifdef CONFIG_LCD static int check_keys(void) { int keys = 0; @@ -235,9 +236,11 @@ static void display_board_info(void) lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix); } +#endif static int mode_leave_menu(int mode) { +#ifdef CONFIG_LCD char *exit_option; char *exit_reset = "reset"; char *exit_back = "back"; @@ -301,8 +304,12 @@ static int mode_leave_menu(int mode) lcd_clear(); return leave; +#else + return 0; +#endif } +#ifdef CONFIG_LCD static void display_download_menu(int mode) { char *selection[BOOT_MODE_EXIT + 1]; @@ -320,9 +327,11 @@ static void display_download_menu(int mode) lcd_printf("\t%s %s - %s\n\n", selection[i], mode_name[i][0], mode_info[i]); } +#endif static void download_menu(void) { +#ifdef CONFIG_LCD int mode = 0; int last_mode = 0; int run; @@ -393,6 +402,7 @@ static void download_menu(void) } lcd_clear(); +#endif } void check_boot_mode(void) diff --git a/board/samsung/espresso7420/Kconfig b/board/samsung/espresso7420/Kconfig new file mode 100644 index 0000000..62251c5 --- /dev/null +++ b/board/samsung/espresso7420/Kconfig @@ -0,0 +1,16 @@ +if TARGET_ESPRESSO7420 + +config SYS_BOARD + default "espresso7420" + help + Espresso7420 is a development/evaluation board for Exynos7420 SoC. + It includes multiple onboard compoments (EMMC/Codec) and various + interconnects (USB/HDMI). + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "espresso7420" + +endif diff --git a/board/samsung/espresso7420/MAINTAINERS b/board/samsung/espresso7420/MAINTAINERS new file mode 100644 index 0000000..aaebc4c --- /dev/null +++ b/board/samsung/espresso7420/MAINTAINERS @@ -0,0 +1,5 @@ +ESPRESSO7420 Board +M: Thomas Abraham <thomas.ab@samsung.com> +S: Maintained +F: board/samsung/espresso7420/ +F: include/configs/espresso7420.h diff --git a/board/samsung/espresso7420/Makefile b/board/samsung/espresso7420/Makefile new file mode 100644 index 0000000..d514dc2 --- /dev/null +++ b/board/samsung/espresso7420/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2016 Samsung Electronics +# Thomas Abraham <thomas.ab@samsung.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SPL_BUILD +obj-y += espresso7420.o +endif diff --git a/board/samsung/espresso7420/espresso7420.c b/board/samsung/espresso7420/espresso7420.c new file mode 100644 index 0000000..04a83bc --- /dev/null +++ b/board/samsung/espresso7420/espresso7420.c @@ -0,0 +1,16 @@ +/* + * Espresso7420 board file + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham <thomas.ab@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int exynos_init(void) +{ + return 0; +} diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 54d01ec..66a54d4 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -596,6 +596,7 @@ int mipi_power(void) return 0; } +#ifdef CONFIG_LCD void exynos_lcd_misc_init(vidinfo_t *vid) { #ifdef CONFIG_TIZEN @@ -606,3 +607,4 @@ void exynos_lcd_misc_init(vidinfo_t *vid) setenv("lcdinfo", "lcd=s6e8ax0"); #endif } +#endif diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 426ae14..81e35b6 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -367,6 +367,7 @@ int exynos_init(void) return 0; } +#ifdef CONFIG_LCD void exynos_lcd_misc_init(vidinfo_t *vid) { #ifdef CONFIG_TIZEN @@ -379,3 +380,4 @@ void exynos_lcd_misc_init(vidinfo_t *vid) setenv("lcdinfo", "lcd=ld9040"); } +#endif diff --git a/board/samtec/vining_fpga/MAINTAINERS b/board/samtec/vining_fpga/MAINTAINERS new file mode 100644 index 0000000..c2002fe --- /dev/null +++ b/board/samtec/vining_fpga/MAINTAINERS @@ -0,0 +1,5 @@ +VINING FPGA BOARD +M: Marek Vasut <marex@denx.de> +S: Maintained +F: include/configs/socfpga_vining_fpga.h +F: configs/socfpga_vining_fpga_defconfig diff --git a/board/samtec/vining_fpga/Makefile b/board/samtec/vining_fpga/Makefile new file mode 100644 index 0000000..86f9b78 --- /dev/null +++ b/board/samtec/vining_fpga/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o diff --git a/board/samtec/vining_fpga/qts/iocsr_config.h b/board/samtec/vining_fpga/qts/iocsr_config.h new file mode 100644 index 0000000..fe5cb61 --- /dev/null +++ b/board/samtec/vining_fpga/qts/iocsr_config.h @@ -0,0 +1,660 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00000000, + 0x300C0000, + 0x000000C0, + 0x00000000, + 0x00000000, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00601806, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x300C0300, + 0x300C0000, + 0x0FF00000, + 0x00000000, + 0x000300C0, + 0x00008000, + 0x18060180, + 0x18060000, + 0x00000000, + 0x00000000, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x00000030, + 0x00000000, + 0x0300C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, + 0x0000C030, + 0x00000000, + 0x03000000, + 0x0000000C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680A28, + 0x41034051, + 0x12481A00, + 0x80A280D0, + 0x34051406, + 0x01A02490, + 0x080D0000, + 0x51406802, + 0x02490340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x49034051, + 0x12481A02, + 0x80A280D0, + 0x34030C06, + 0x01A00040, + 0x280D0002, + 0x5140680A, + 0x02490340, + 0xD012481A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8A28A3D5, + 0xF6D1451E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x05140680, + 0xD569A47A, + 0x1E8A28A3, + 0x48F6D145, + 0x00035292, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8A28A3D5, + 0xF4D1451E, + 0x034AD348, + 0x821A0186, + 0x0000D000, + 0x00000680, + 0xD569A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x0C864000, + 0x59647A03, + 0xCB2CA3DD, + 0xF6D9651E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDD59647A, + 0x1E8A28A3, + 0x48F6D965, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F16080, + 0x1A041404, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xF228A3D5, + 0xF4D1451E, + 0x03529248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8A28A3, + 0x48F6D145, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/qts/pinmux_config.h b/board/samtec/vining_fpga/qts/pinmux_config.h new file mode 100644 index 0000000..9680365 --- /dev/null +++ b/board/samtec/vining_fpga/qts/pinmux_config.h @@ -0,0 +1,219 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 2, /* FLASHIO0 */ + 2, /* FLASHIO1 */ + 2, /* FLASHIO2 */ + 2, /* FLASHIO3 */ + 2, /* FLASHIO4 */ + 2, /* FLASHIO5 */ + 2, /* FLASHIO6 */ + 2, /* FLASHIO7 */ + 2, /* FLASHIO8 */ + 2, /* FLASHIO9 */ + 2, /* FLASHIO10 */ + 2, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 2, /* GENERALIO15 */ + 2, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 2, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 1, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 1, /* SPIS1USEFPGA */ + 1, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/qts/pll_config.h b/board/samtec/vining_fpga/qts/pll_config.h new file mode 100644 index 0000000..c8a6e96 --- /dev/null +++ b/board/samtec/vining_fpga/qts/pll_config.h @@ -0,0 +1,91 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 488281 +#define CONFIG_HPS_CLK_SDMMC_HZ 1953125 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 12500000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/qts/sdram_config.h b/board/samtec/vining_fpga/qts/sdram_config.h new file mode 100644 index 0000000..74cb405 --- /dev/null +++ b/board/samtec/vining_fpga/qts/sdram_config.h @@ -0,0 +1,341 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 7 +#define CALIB_VFIFO_OFFSET 5 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080421, + 0x10080520, + 0x10090046, + 0x100a0088, + 0x100b0000, + 0x10380400, + 0x10080441, + 0x100804c0, + 0x100a0026, + 0x10090110, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c new file mode 100644 index 0000000..f3a92b5 --- /dev/null +++ b/board/samtec/vining_fpga/socfpga.c @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ +int board_late_init(void) +{ + const unsigned int phy_nrst_gpio = 0; + const unsigned int usb_nrst_gpio = 35; + int ret; + + status_led_set(1, STATUS_LED_ON); + status_led_set(2, STATUS_LED_ON); + + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio"); + if (!ret) + gpio_direction_output(phy_nrst_gpio, 1); + else + printf("Cannot remove PHY from reset!\n"); + + ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio"); + if (!ret) + gpio_direction_output(usb_nrst_gpio, 1); + else + printf("Cannot remove USB from reset!\n"); + + mdelay(50); + + return 0; +} + +#ifndef CONFIG_SPL_BUILD +int misc_init_r(void) +{ + uchar data[128]; + char str[32]; + u32 serial; + int ret; + + /* EEPROM is at bus 0. */ + ret = i2c_set_bus_num(0); + if (ret) { + puts("Cannot select EEPROM I2C bus.\n"); + return 0; + } + + /* EEPROM is at address 0x50. */ + ret = eeprom_read(0x50, 0, data, sizeof(data)); + if (ret) { + puts("Cannot read I2C EEPROM.\n"); + return 0; + } + + /* Check EEPROM signature. */ + if (!(data[0] == 0xa5 && data[1] == 0x5a)) { + puts("Invalid I2C EEPROM signature.\n"); + setenv("unit_serial", "invalid"); + setenv("unit_ident", "VINing-xxxx-STD"); + setenv("hostname", "vining-invalid"); + return 0; + } + + /* If 'unit_serial' is already set, do nothing. */ + if (!getenv("unit_serial")) { + /* This field is Big Endian ! */ + serial = (data[0x54] << 24) | (data[0x55] << 16) | + (data[0x56] << 8) | (data[0x57] << 0); + memset(str, 0, sizeof(str)); + sprintf(str, "%07i", serial); + setenv("unit_serial", str); + } + + if (!getenv("unit_ident")) { + memset(str, 0, sizeof(str)); + memcpy(str, &data[0x2e], 18); + setenv("unit_ident", str); + } + + /* Set ethernet address from EEPROM. */ + if (!getenv("ethaddr") && is_valid_ethaddr(&data[0x62])) + eth_setenv_enetaddr("ethaddr", &data[0x62]); + + return 0; +} +#endif diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox index fa1842b..9fe3bf1 100644 --- a/board/sandbox/README.sandbox +++ b/board/sandbox/README.sandbox @@ -186,8 +186,7 @@ U-Boot sandbox supports these emulations: A wide range of commands is implemented. Filesystems which use a block device are supported. -Also sandbox uses generic board (CONFIG_SYS_GENERIC_BOARD) and supports -driver model (CONFIG_DM) and associated commands. +Also sandbox supports driver model (CONFIG_DM) and associated commands. Linux RAW Networking Bridge diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index c127f6c..9cafcea 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -83,8 +83,12 @@ int board_init(void) #ifdef CONFIG_FACTORYSET factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR); #endif + gpmc_init(); +#ifdef CONFIG_NAND_CS_INIT + board_nand_cs_init(); +#endif #ifdef CONFIG_VIDEO board_video_init(); #endif diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig index 819d187..a699c7d 100644 --- a/board/siemens/draco/Kconfig +++ b/board/siemens/draco/Kconfig @@ -45,3 +45,19 @@ config SYS_CONFIG_NAME default "rastaban" endif + +if TARGET_ETAMIN + +config SYS_BOARD + default "draco" + +config SYS_VENDOR + default "siemens" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "etamin" + +endif diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS index 484dd73..e9107f0 100644 --- a/board/siemens/draco/MAINTAINERS +++ b/board/siemens/draco/MAINTAINERS @@ -4,6 +4,7 @@ S: Maintained F: board/siemens/draco/ F: include/configs/draco.h F: configs/draco_defconfig +F: configs/etamin_defconfig F: include/configs/thuban.h F: configs/thuban_defconfig F: include/configs/rastaban.h diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index 988c12a..d8869a0 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -24,6 +24,7 @@ #include <asm/arch/gpio.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> #include <asm/io.h> #include <asm/emif.h> #include <asm/gpio.h> @@ -33,6 +34,7 @@ #include <watchdog.h> #include "board.h" #include "../common/factoryset.h" +#include <nand.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,6 +42,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct draco_baseboard_id __attribute__((section(".data"))) settings; #if DDR_PLL_FREQ == 303 +#if !defined(CONFIG_TARGET_ETAMIN) /* Default@303MHz-i0 */ const struct ddr3_data ddr3_default = { 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F, @@ -48,6 +51,16 @@ const struct ddr3_data ddr3_default = { "default name @303MHz \0", "default marking \0", }; +#else +/* etamin board */ +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F, + 0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2, + 0x0000093B, 0x0000018A, + "test-etamin \0", + "generic-8Gbit \0", +}; +#endif #elif DDR_PLL_FREQ == 400 /* Default@400MHz-i0 */ const struct ddr3_data ddr3_default = { @@ -105,6 +118,40 @@ static void print_chip_data(void) } #endif /* CONFIG_SPL_BUILD */ +#define AM335X_NAND_ECC_MASK 0x0f +#define AM335X_NAND_ECC_TYPE_16 0x02 + +static int ecc_type; + +struct am335x_nand_geometry { + u32 magic; + u8 nand_geo_addr; + u8 nand_geo_page; + u8 nand_bus; +}; + +static int draco_read_nand_geometry(void) +{ + struct am335x_nand_geometry geo; + + /* Read NAND geometry */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2, + (uchar *)&geo, sizeof(struct am335x_nand_geometry))) { + printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n"); + return -EIO; + } + if (geo.magic != 0xa657b310) { + printf("%s: bad magic: %x\n", __func__, geo.magic); + return -EFAULT; + } + if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16) + ecc_type = 16; + else + ecc_type = 8; + + return 0; +} + /* * Read header information from EEPROM into global structure. */ @@ -147,6 +194,8 @@ static int read_eeprom(void) printf("Warning: No chip data in eeprom\n"); print_ddr3_timings(); + + return draco_read_nand_geometry(); #endif return 0; } @@ -174,6 +223,7 @@ struct ctrl_ioregs draco_ddr3_ioregs = { draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = settings.ddr3.emif_ddr_phy_ctlr_1; draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config; + draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000; draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0; @@ -207,7 +257,18 @@ static void spl_siemens_board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { - omap_nand_switch_ecc(1, 8); + int ret; + + ret = draco_read_nand_geometry(); + if (ret != 0) + return ret; + + nand_curr_device = 0; + omap_nand_switch_ecc(1, ecc_type); +#ifdef CONFIG_TARGET_ETAMIN + nand_curr_device = 1; + omap_nand_switch_ecc(1, ecc_type); +#endif #ifdef CONFIG_FACTORYSET /* Set ASN in environment*/ if (factory_dat.asn[0] != 0) { @@ -283,7 +344,7 @@ int board_eth_init(bd_t *bis) } static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) + char *const argv[]) { /* Reset SMSC LAN9303 switch for default configuration */ gpio_request(GPIO_LAN9303_NRST, "nRST"); @@ -303,4 +364,23 @@ U_BOOT_CMD( #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ +#ifdef CONFIG_NAND_CS_INIT +/* GPMC definitions for second nand cs1 */ +static const u32 gpmc_nand_config[] = { + ETAMIN_NAND_GPMC_CONFIG1, + ETAMIN_NAND_GPMC_CONFIG2, + ETAMIN_NAND_GPMC_CONFIG3, + ETAMIN_NAND_GPMC_CONFIG4, + ETAMIN_NAND_GPMC_CONFIG5, + ETAMIN_NAND_GPMC_CONFIG6, + /*CONFIG7- computed as params */ +}; + +static void board_nand_cs_init(void) +{ + enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1], + 0x18000000, GPMC_SIZE_16M); +} +#endif + #include "../common/board.c" diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c index dbcc80b..38a484e 100644 --- a/board/siemens/draco/mux.c +++ b/board/siemens/draco/mux.c @@ -51,6 +51,7 @@ static struct module_pin_mux nand_pin_mux[] = { {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_csn1), MODE(0) | PULLUDEN | PULLUP_EN}, /* NAND_CS1 */ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ @@ -68,7 +69,6 @@ static struct module_pin_mux gpios_pin_mux[] = { {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/ {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/ /* Triacs initial HW Rev */ - {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */ {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */ {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */ {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */ diff --git a/board/socrates/nand.c b/board/socrates/nand.c index 15e6ea6..a67d812 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -48,7 +48,7 @@ static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte) static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) { int i; - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); for (i = 0; i < len; i++) { out_be32(this->IO_ADDR_W, @@ -88,7 +88,7 @@ static u16 sc_nand_read_word(struct mtd_info *mtd) static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) { int i; - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int val; val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ; @@ -105,7 +105,7 @@ static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) */ static int sc_nand_device_ready(struct mtd_info *mtdinfo) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY) return 0; /* busy */ diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 953a43f..8b34a80 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -217,7 +217,7 @@ int board_early_init_r (void) } #endif /* CONFIG_BOARD_EARLY_INIT_R */ -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { u32 val[12]; @@ -253,7 +253,7 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* CONFIG_OF_BOARD_SETUP */ #define DEFAULT_BRIGHTNESS 25 #define BACKLIGHT_ENABLE (1 << 31) diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c index b8edfcd..f8e9fdd 100644 --- a/board/spear/x600/x600.c +++ b/board/spear/x600/x600.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <micrel.h> #include <nand.h> #include <netdev.h> #include <phy.h> @@ -69,27 +70,64 @@ void board_nand_init(void) int board_phy_config(struct phy_device *phydev) { - /* Extended PHY control 1, select GMII */ - phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); - - /* Software reset necessary after GMII mode selction */ - phy_reset(phydev); - - /* Enable extended page register access */ - phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); - - /* 17e: Enhanced LED behavior, needs to be written twice */ - phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); - phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); - - /* 16e: Enhanced LED method select */ - phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); - - /* Disable extended page register access */ - phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); - - /* Enable clock output pin */ - phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); + unsigned short id1, id2; + + /* check whether KSZ9031 or AR8035 has to be configured */ + id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); + id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); + + if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { + /* PHY configuration for Micrel KSZ9031 */ + printf("PHY KSZ9031 detected - "); + + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); + + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x03FF); + } else { + /* PHY configuration for Vitesse VSC8641 */ + printf("PHY VSC8641 detected - "); + + /* Extended PHY control 1, select GMII */ + phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); + + /* Software reset necessary after GMII mode selction */ + phy_reset(phydev); + + /* Enable extended page register access */ + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); + + /* 17e: Enhanced LED behavior, needs to be written twice */ + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + + /* 16e: Enhanced LED method select */ + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); + + /* Disable extended page register access */ + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); + + /* Enable clock output pin */ + phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); + } if (phydev->drv->config) phydev->drv->config(phydev); diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index fa78720..c1ae6f5 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -18,7 +18,6 @@ config SUNXI_GEN_SUN6I choice prompt "Sunxi SoC Variant" - optional config MACH_SUN4I bool "sun4i (Allwinner A10)" @@ -68,6 +67,12 @@ config MACH_SUN8I_A33 select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT +config MACH_SUN8I_A83T + bool "sun8i (Allwinner A83T)" + select CPU_V7 + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + config MACH_SUN8I_H3 bool "sun8i (Allwinner H3)" select CPU_V7 @@ -77,22 +82,16 @@ config MACH_SUN8I_H3 select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT -config MACH_SUN50I - bool "sun50i (Allwinner A64)" - select ARM64 - select SUNXI_GEN_SUN6I - -config MACH_SUN8I_A83T - bool "sun8i (Allwinner A83T)" - select CPU_V7 - select SUNXI_GEN_SUN6I - select SUPPORT_SPL - config MACH_SUN9I bool "sun9i (Allwinner A80)" select CPU_V7 select SUNXI_GEN_SUN6I +config MACH_SUN50I + bool "sun50i (Allwinner A64)" + select ARM64 + select SUNXI_GEN_SUN6I + endchoice # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" @@ -261,6 +260,7 @@ config MMC config MMC0_CD_PIN string "Card detect pin for mmc0" + default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I default "" ---help--- Set the card detect pin for mmc0, leave empty to not use cd. This @@ -368,6 +368,7 @@ config I2C0_ENABLE bool "Enable I2C/TWI controller 0" default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I default n if MACH_SUN6I || MACH_SUN8I + select CMD_I2C ---help--- This allows enabling I2C/TWI controller 0 by muxing its pins, enabling its clock and setting up the bus. This is especially useful on devices @@ -377,12 +378,14 @@ config I2C0_ENABLE config I2C1_ENABLE bool "Enable I2C/TWI controller 1" default n + select CMD_I2C ---help--- See I2C0_ENABLE help text. config I2C2_ENABLE bool "Enable I2C/TWI controller 2" default n + select CMD_I2C ---help--- See I2C0_ENABLE help text. @@ -390,6 +393,7 @@ if MACH_SUN6I || MACH_SUN7I config I2C3_ENABLE bool "Enable I2C/TWI controller 3" default n + select CMD_I2C ---help--- See I2C0_ENABLE help text. endif @@ -399,6 +403,7 @@ config R_I2C_ENABLE bool "Enable the PRCM I2C/TWI controller" # This is used for the pmic on H3 default y if SY8106A_POWER + select CMD_I2C ---help--- Set this to y to enable the I2C controller which is part of the PRCM. endif @@ -407,6 +412,7 @@ if MACH_SUN7I config I2C4_ENABLE bool "Enable I2C/TWI controller 4" default n + select CMD_I2C ---help--- See I2C0_ENABLE help text. endif @@ -419,7 +425,7 @@ config AXP_GPIO config VIDEO boolean "Enable graphical uboot console on HDMI, LCD or VGA" - depends on !MACH_SUN8I_A83T + depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I_A64 default y ---help--- Say Y here to add support for using a cfb console on the HDMI, LCD @@ -535,6 +541,7 @@ config VIDEO_LCD_PANEL_I2C bool "LCD panel needs to be configured via i2c" depends on VIDEO default n + select CMD_I2C ---help--- Say y here if the LCD panel needs to be configured via i2c. This will add a bitbang i2c controller using gpios to talk to the LCD. diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 3cf3614..d09cf6d 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -133,15 +133,6 @@ int dram_init(void) return 0; } -#ifdef CONFIG_MACH_SUN50I -void dram_init_banksize(void) -{ - /* We need to reserve the first 16MB of RAM for ATF */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024); - gd->bd->bi_dram[0].size = get_effective_memsize() - (16 * 1024 * 1024); -} -#endif - #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) static void nand_pinmux_setup(void) { @@ -483,10 +474,12 @@ void sunxi_board_init(void) #endif #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ - defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER + defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ + defined CONFIG_AXP818_POWER power_failed = axp_init(); -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ + defined CONFIG_AXP818_POWER power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); #endif power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); @@ -494,11 +487,13 @@ void sunxi_board_init(void) #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); #endif -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ + defined CONFIG_AXP818_POWER power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); #endif -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ + defined CONFIG_AXP818_POWER power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); #endif power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); @@ -509,11 +504,14 @@ void sunxi_board_init(void) power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); #endif -#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER) +#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ + defined(CONFIG_AXP818_POWER) power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); +#if !defined CONFIG_AXP809_POWER power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); +#endif power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); @@ -524,6 +522,10 @@ void sunxi_board_init(void) power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); #endif + +#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER + power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); +#endif #endif printf("DRAM:"); ramsize = sunxi_dram_init(); diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS index 7dc2b83..c99e06d 100644 --- a/board/ti/am335x/MAINTAINERS +++ b/board/ti/am335x/MAINTAINERS @@ -6,7 +6,6 @@ F: include/configs/am335x_evm.h F: configs/am335x_boneblack_defconfig F: configs/am335x_boneblack_vboot_defconfig F: configs/am335x_evm_defconfig -F: configs/am335x_gp_evm_defconfig F: configs/am335x_evm_nor_defconfig F: configs/am335x_evm_norboot_defconfig F: configs/am335x_evm_spiboot_defconfig diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 4330be6..56f4984 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -11,11 +11,13 @@ #include <common.h> #include <errno.h> #include <spl.h> +#include <serial.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> #include <asm/arch/omap.h> #include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> +#include <asm/arch/clk_synthesizer.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> @@ -37,7 +39,13 @@ DECLARE_GLOBAL_DATA_PTR; /* GPIO that controls power to DDR on EVM-SK */ -#define GPIO_DDR_VTT_EN 7 +#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) +#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7) +#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18) +#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4) +#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) +#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) +#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) #if defined(CONFIG_SPL_BUILD) || \ (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH)) @@ -52,6 +60,16 @@ static inline int __maybe_unused read_eeprom(void) return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR); } +#ifndef CONFIG_DM_SERIAL +struct serial_device *default_serial_console(void) +{ + if (board_is_icev2()) + return &eserial4_device; + else + return &eserial1_device; +} +#endif + #ifndef CONFIG_SKIP_LOWLEVEL_INIT static const struct ddr_data ddr2_data = { .datardsratio0 = MT47H128M16RT25E_RD_DQS, @@ -97,6 +115,13 @@ static const struct ddr_data ddr3_evm_data = { .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, }; +static const struct ddr_data ddr3_icev2_data = { + .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz, + .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz, + .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz, + .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz, +}; + static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41J128MJT125_RATIO, .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, @@ -130,6 +155,17 @@ static const struct cmd_control ddr3_evm_cmd_ctrl_data = { .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, }; +static const struct cmd_control ddr3_icev2_cmd_ctrl_data = { + .cmd0csratio = MT41J128MJT125_RATIO_400MHz, + .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, + + .cmd1csratio = MT41J128MJT125_RATIO_400MHz, + .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, + + .cmd2csratio = MT41J128MJT125_RATIO_400MHz, + .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, +}; + static struct emif_regs ddr3_emif_reg_data = { .sdram_config = MT41J128MJT125_EMIF_SDCFG, .ref_ctrl = MT41J128MJT125_EMIF_SDREF, @@ -162,6 +198,17 @@ static struct emif_regs ddr3_evm_emif_reg_data = { PHY_EN_DYN_PWRDN, }; +static struct emif_regs ddr3_icev2_emif_reg_data = { + .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz, + .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz, + .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz, + .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz, + .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz, + .zq_config = MT41J128MJT125_ZQ_CFG_400MHz, + .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz | + PHY_EN_DYN_PWRDN, +}; + #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { @@ -339,7 +386,7 @@ const struct dpll_params *get_dpll_ddr_params(void) if (board_is_evm_sk()) return &dpll_ddr_evm_sk; - else if (board_is_bone_lt()) + else if (board_is_bone_lt() || board_is_icev2()) return &dpll_ddr_bone_black; else if (board_is_evm_15_or_later()) return &dpll_ddr_evm_sk; @@ -418,6 +465,11 @@ void sdram_init(void) gpio_direction_output(GPIO_DDR_VTT_EN, 1); } + if (board_is_icev2()) { + gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1); + } + if (board_is_evm_sk()) config_ddr(303, &ioregs_evmsk, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); @@ -429,12 +481,59 @@ void sdram_init(void) else if (board_is_evm_15_or_later()) config_ddr(303, &ioregs_evm15, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); + else if (board_is_icev2()) + config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data, + &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, + 0); else config_ddr(266, &ioregs, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); } #endif +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void request_and_set_gpio(int gpio, char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret < 0) { + printf("%s: Unable to request %s\n", __func__, name); + return; + } + + ret = gpio_direction_output(gpio, 0); + if (ret < 0) { + printf("%s: Unable to set %s as output\n", __func__, name); + goto err_free_gpio; + } + + gpio_set_value(gpio, 1); + + return; + +err_free_gpio: + gpio_free(gpio); +} + +#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N); + +/** + * RMII mode on ICEv2 board needs 50MHz clock. Given the clock + * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle + * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to + * give 50MHz output for Eth0 and 1. + */ +static struct clk_synth cdce913_data = { + .id = 0x81, + .capacitor = 0x90, + .mux = 0x6d, + .pdiv2 = 0x2, + .pdiv3 = 0x2, +}; +#endif + /* * Basic board specific setup. Pinmux has been handled already. */ @@ -448,6 +547,23 @@ int board_init(void) #if defined(CONFIG_NOR) || defined(CONFIG_NAND) gpmc_init(); #endif +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) + int rv; + + if (board_is_icev2()) { + REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); + REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL); + REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); + REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); + + rv = setup_clock_synthesizer(&cdce913_data); + if (rv) { + printf("Clock synthesizer setup failed %d\n", rv); + return rv; + } + } +#endif + return 0; } @@ -515,6 +631,12 @@ static struct cpsw_platform_data cpsw_data = { }; #endif +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\ + defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) + /* * This function will: * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr @@ -526,11 +648,6 @@ static struct cpsw_platform_data cpsw_data = { * Build in only these cases to avoid warnings about unused variables * when we build an SPL that has neither option but full U-Boot will. */ -#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ - && defined(CONFIG_SPL_BUILD)) || \ - ((defined(CONFIG_DRIVER_TI_CPSW) || \ - defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \ - !defined(CONFIG_SPL_BUILD)) int board_eth_init(bd_t *bis) { int rv, n = 0; @@ -581,6 +698,12 @@ int board_eth_init(bd_t *bis) writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; + } else if (board_is_icev2()) { + writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; + cpsw_slaves[0].phy_addr = 1; + cpsw_slaves[1].phy_addr = 3; } else { writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = @@ -632,3 +755,23 @@ int board_eth_init(bd_t *bis) #endif #endif /* CONFIG_DM_ETH */ + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (board_is_gp_evm() && !strcmp(name, "am335x-evm")) + return 0; + else if (board_is_bone() && !strcmp(name, "am335x-bone")) + return 0; + else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack")) + return 0; + else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk")) + return 0; + else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen")) + return 0; + else if (board_is_icev2() && !strcmp(name, "am335x-icev2")) + return 0; + else + return -1; +} +#endif diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h index 062c345..9776df7 100644 --- a/board/ti/am335x/board.h +++ b/board/ti/am335x/board.h @@ -47,6 +47,11 @@ static inline int board_is_evm_15_or_later(void) strncmp("1.5", board_ti_get_rev(), 3) <= 0); } +static inline int board_is_icev2(void) +{ + return board_ti_is("A335_ICE") && !strncmp("2", board_ti_get_rev(), 1); +} + /* * We have three pin mux functions that must exist. We must be able to enable * uart0, for initial output and i2c0 to read the main EEPROM. We then have a diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index fdf827f..8afa5f9 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -135,6 +135,11 @@ static struct module_pin_mux gpio0_7_pin_mux[] = { {-1}, }; +static struct module_pin_mux gpio0_18_pin_mux[] = { + {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)}, /* GPIO0_18 */ + {-1}, +}; + static struct module_pin_mux rgmii1_pin_mux[] = { {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ @@ -172,6 +177,20 @@ static struct module_pin_mux mii1_pin_mux[] = { {-1}, }; +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */ + {OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */ + {-1}, +}; + #ifdef CONFIG_NAND static struct module_pin_mux nand_pin_mux[] = { {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ @@ -237,6 +256,12 @@ static struct module_pin_mux bone_norcape_pin_mux[] = { }; #endif +static struct module_pin_mux uart3_icev2_pin_mux[] = { + {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(mii1_rxd2), MODE(1) | PULLUDEN}, /* UART3_TXD */ + {-1}, +}; + #if defined(CONFIG_NOR_BOOT) void enable_norboot_pin_mux(void) { @@ -365,6 +390,12 @@ void enable_board_pin_mux(void) #else configure_module_pin_mux(mmc1_pin_mux); #endif + } else if (board_is_icev2()) { + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(gpio0_18_pin_mux); + configure_module_pin_mux(uart3_icev2_pin_mux); + configure_module_pin_mux(rmii1_pin_mux); + configure_module_pin_mux(spi0_pin_mux); } else { puts("Unknown board, cannot configure pinmux."); hang(); diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS index 96ef85b..3d40b17 100644 --- a/board/ti/am43xx/MAINTAINERS +++ b/board/ti/am43xx/MAINTAINERS @@ -7,5 +7,3 @@ F: configs/am43xx_evm_defconfig F: configs/am43xx_evm_qspiboot_defconfig F: configs/am43xx_evm_ethboot_defconfig F: configs/am43xx_evm_usbhost_boot_defconfig -F: configs/am437x_gp_evm_defconfig -F: configs/am437x_sk_evm_defconfig diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index d208d2f..bde5ac7 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -341,7 +341,7 @@ const struct dpll_params *get_dpll_ddr_params(void) if (board_is_eposevm()) return &epos_evm_dpll_ddr[ind]; - else if (board_is_gpevm() || board_is_sk()) + else if (board_is_evm() || board_is_sk()) return &gp_evm_dpll_ddr; else if (board_is_idk()) return &idk_dpll_ddr; @@ -553,7 +553,7 @@ void sdram_init(void) enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz_beta, 0); - } else if (board_is_gpevm()) { + } else if (board_is_evm()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz, 0); @@ -678,71 +678,71 @@ static struct ti_usb_phy_device usb_phy2_device = { .index = 1, }; +int usb_gadget_handle_interrupts(int index) +{ + u32 status; + + status = dwc3_omap_uboot_interrupt_status(index); + if (status) + dwc3_uboot_handle_interrupt(index); + + return 0; +} +#endif /* CONFIG_USB_DWC3 */ + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) int board_usb_init(int index, enum usb_init_type init) { enable_usb_clocks(index); +#ifdef CONFIG_USB_DWC3 switch (index) { case 0: if (init == USB_INIT_DEVICE) { usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; - } else { - usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; - usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; + dwc3_omap_uboot_init(&usb_otg_ss1_glue); + ti_usb_phy_uboot_init(&usb_phy1_device); + dwc3_uboot_init(&usb_otg_ss1); } - - dwc3_omap_uboot_init(&usb_otg_ss1_glue); - ti_usb_phy_uboot_init(&usb_phy1_device); - dwc3_uboot_init(&usb_otg_ss1); break; case 1: if (init == USB_INIT_DEVICE) { usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; - } else { - usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; - usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; + ti_usb_phy_uboot_init(&usb_phy2_device); + dwc3_omap_uboot_init(&usb_otg_ss2_glue); + dwc3_uboot_init(&usb_otg_ss2); } - - ti_usb_phy_uboot_init(&usb_phy2_device); - dwc3_omap_uboot_init(&usb_otg_ss2_glue); - dwc3_uboot_init(&usb_otg_ss2); break; default: printf("Invalid Controller Index\n"); } +#endif return 0; } int board_usb_cleanup(int index, enum usb_init_type init) { +#ifdef CONFIG_USB_DWC3 switch (index) { case 0: case 1: - ti_usb_phy_uboot_exit(index); - dwc3_uboot_exit(index); - dwc3_omap_uboot_exit(index); + if (init == USB_INIT_DEVICE) { + ti_usb_phy_uboot_exit(index); + dwc3_uboot_exit(index); + dwc3_omap_uboot_exit(index); + } break; default: printf("Invalid Controller Index\n"); } +#endif disable_usb_clocks(index); return 0; } - -int usb_gadget_handle_interrupts(int index) -{ - u32 status; - - status = dwc3_omap_uboot_interrupt_status(index); - if (status) - dwc3_uboot_handle_interrupt(index); - - return 0; -} -#endif +#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ #ifdef CONFIG_DRIVER_TI_CPSW @@ -846,3 +846,19 @@ int board_eth_init(bd_t *bis) return rv; } #endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (board_is_gpevm() && !strcmp(name, "am437x-gp-evm")) + return 0; + else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) + return 0; + else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) + return 0; + else if (board_is_idk() && !strcmp(name, "am437x-idk-evm")) + return 0; + else + return -1; +} +#endif diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 2cf7a77..3f93d13 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -37,14 +37,24 @@ static inline int board_is_idk(void) return board_ti_is("AM43_IDK"); } +static inline int board_is_hsevm(void) +{ + return board_ti_is("AM43XXHS"); +} + +static inline int board_is_evm(void) +{ + return board_is_gpevm() || board_is_hsevm(); +} + static inline int board_is_evm_14_or_later(void) { - return (board_is_gpevm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0); + return board_is_evm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0; } static inline int board_is_evm_12_or_later(void) { - return (board_is_gpevm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0); + return board_is_evm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0; } void enable_uart0_pin_mux(void); diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index e03b1bc..f26b21e 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -126,7 +126,7 @@ void enable_board_pin_mux(void) configure_module_pin_mux(i2c0_pin_mux); configure_module_pin_mux(mdio_pin_mux); - if (board_is_gpevm()) { + if (board_is_evm()) { configure_module_pin_mux(gpio5_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); #if defined(CONFIG_NAND) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 86b8f6e..ccf97b2 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -63,28 +63,28 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) } static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { - .sdram_config_init = 0x61851b32, - .sdram_config = 0x61851b32, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x000040F1, - .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xcccf36ab, - .sdram_tim2 = 0x308f7fda, - .sdram_tim3 = 0x409f88a8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x5007190b, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400b, - .emif_ddr_phy_ctlr_1 = 0x0e24400b, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00910091, - .emif_ddr_ext_phy_ctrl_3 = 0x00950095, - .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, - .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 + .sdram_config_init = 0x61851b32, + .sdram_config = 0x61851b32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xcccf36ab, + .sdram_tim2 = 0x308f7fda, + .sdram_tim3 = 0x409f88a8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, + .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 }; /* Ext phy ctrl regs 1-35 */ @@ -127,28 +127,28 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { }; static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { - .sdram_config_init = 0x61851b32, - .sdram_config = 0x61851b32, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x000040F1, - .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xcccf36b3, - .sdram_tim2 = 0x308f7fda, - .sdram_tim3 = 0x407f88a8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x5007190b, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400b, - .emif_ddr_phy_ctlr_1 = 0x0e24400b, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00910091, - .emif_ddr_ext_phy_ctrl_3 = 0x00950095, - .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, - .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 + .sdram_config_init = 0x61851b32, + .sdram_config = 0x61851b32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xcccf36b3, + .sdram_tim2 = 0x308f7fda, + .sdram_tim3 = 0x407f88a8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, + .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 }; static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { @@ -216,41 +216,77 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) } struct vcores_data beagle_x15_volts = { - .mpu.value = VDD_MPU_DRA752, - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.value = VDD_MPU_DRA7, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS659038_REG_ADDR_SMPS12, .mpu.pmic = &tps659038, - .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, - .eve.value = VDD_EVE_DRA752, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.value = VDD_EVE_DRA7, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS659038_REG_ADDR_SMPS45, .eve.pmic = &tps659038, .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, - .gpu.value = VDD_GPU_DRA752, - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.value = VDD_GPU_DRA7, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS659038_REG_ADDR_SMPS45, .gpu.pmic = &tps659038, .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, - .core.value = VDD_CORE_DRA752, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.value = VDD_CORE_DRA7, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, .core.addr = TPS659038_REG_ADDR_SMPS6, .core.pmic = &tps659038, - .iva.value = VDD_IVA_DRA752, - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.value = VDD_IVA_DRA7, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS659038_REG_ADDR_SMPS45, .iva.pmic = &tps659038, .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, }; +struct vcores_data am572x_idk_volts = { + .mpu.value = VDD_MPU_DRA7, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, + .mpu.pmic = &tps659038, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + + .eve.value = VDD_EVE_DRA7, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45, + .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, + + .gpu.value = VDD_GPU_DRA7, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS6, + .gpu.pmic = &tps659038, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, + + .core.value = VDD_CORE_DRA7, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS7, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA7, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS8, + .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, +}; + #ifdef CONFIG_SPL_BUILD /* No env to setup for SPL */ static inline void setup_board_eeprom_env(void) { } @@ -315,11 +351,18 @@ invalid_eeprom: #endif /* CONFIG_SPL_BUILD */ +void vcores_init(void) +{ + if (board_is_am572x_idk()) + *omap_vcores = &am572x_idk_volts; + else + *omap_vcores = &beagle_x15_volts; +} + void hw_data_init(void) { *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; - *omap_vcores = &beagle_x15_volts; *ctrl = &dra7xx_ctrl; } @@ -439,6 +482,19 @@ static struct ti_usb_phy_device usb_phy2_device = { .index = 1, }; +int usb_gadget_handle_interrupts(int index) +{ + u32 status; + + status = dwc3_omap_uboot_interrupt_status(index); + if (status) + dwc3_uboot_handle_interrupt(index); + + return 0; +} +#endif /* CONFIG_USB_DWC3 */ + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) int board_usb_init(int index, enum usb_init_type init) { enable_usb_clocks(index); @@ -448,31 +504,23 @@ int board_usb_init(int index, enum usb_init_type init) printf("port %d can't be used as device\n", index); disable_usb_clocks(index); return -EINVAL; - } else { - usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; - usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; - setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, - OTG_SS_CLKCTRL_MODULEMODE_HW | - OPTFCLKEN_REFCLK960M); } - - ti_usb_phy_uboot_init(&usb_phy1_device); - dwc3_omap_uboot_init(&usb_otg_ss1_glue); - dwc3_uboot_init(&usb_otg_ss1); break; case 1: if (init == USB_INIT_DEVICE) { +#ifdef CONFIG_USB_DWC3 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; + ti_usb_phy_uboot_init(&usb_phy2_device); + dwc3_omap_uboot_init(&usb_otg_ss2_glue); + dwc3_uboot_init(&usb_otg_ss2); +#endif } else { printf("port %d can't be used as host\n", index); disable_usb_clocks(index); return -EINVAL; } - ti_usb_phy_uboot_init(&usb_phy2_device); - dwc3_omap_uboot_init(&usb_otg_ss2_glue); - dwc3_uboot_init(&usb_otg_ss2); break; default: printf("Invalid Controller Index\n"); @@ -483,31 +531,24 @@ int board_usb_init(int index, enum usb_init_type init) int board_usb_cleanup(int index, enum usb_init_type init) { +#ifdef CONFIG_USB_DWC3 switch (index) { case 0: case 1: - ti_usb_phy_uboot_exit(index); - dwc3_uboot_exit(index); - dwc3_omap_uboot_exit(index); + if (init == USB_INIT_DEVICE) { + ti_usb_phy_uboot_exit(index); + dwc3_uboot_exit(index); + dwc3_omap_uboot_exit(index); + } break; default: printf("Invalid Controller Index\n"); } +#endif disable_usb_clocks(index); return 0; } - -int usb_gadget_handle_interrupts(int index) -{ - u32 status; - - status = dwc3_omap_uboot_interrupt_status(index); - if (status) - dwc3_uboot_handle_interrupt(index); - - return 0; -} -#endif +#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ #ifdef CONFIG_DRIVER_TI_CPSW @@ -686,3 +727,12 @@ int board_early_init_f(void) return 0; } #endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + + return 0; +} +#endif diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS index 3f638d0..46b6e82 100644 --- a/board/ti/dra7xx/MAINTAINERS +++ b/board/ti/dra7xx/MAINTAINERS @@ -3,8 +3,5 @@ M: Lokesh Vutla <lokeshvutla@ti.com> S: Maintained F: board/ti/dra7xx/ F: include/configs/dra7xx_evm.h -F: configs/dra72_evm_defconfig -F: configs/dra74_evm_defconfig F: configs/dra7xx_evm_defconfig -F: configs/dra7xx_evm_qspiboot_defconfig -F: configs/dra7xx_evm_uart3_defconfig +F: configs/dra7xx_hs_evm_defconfig diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 9bd71d8..3fbbc9b 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -718,3 +718,24 @@ int board_early_init_f(void) return 0; } #endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (is_dra72x() && !strcmp(name, "dra72-evm")) + return 0; + else if (!is_dra72x() && !strcmp(name, "dra7-evm")) + return 0; + else + return -1; +} +#endif diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 9e8ad93..1de7df0 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -131,7 +131,7 @@ u32 spl_boot_device(void) } #endif -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { int lpae; @@ -273,4 +273,4 @@ void ft_board_setup_ex(void *blob, bd_t *bd) ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE); } -#endif +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index b62c412..8f16845 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -117,12 +117,28 @@ int board_mmc_init(bd_t *bis) #endif #ifdef CONFIG_BOARD_EARLY_INIT_F + +static void k2g_reset_mux_config(void) +{ + /* Unlock the reset mux register */ + clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); + + /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */ + clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK, + RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT); + + /* lock the reset mux register to prevent any spurious writes. */ + setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); +} + int board_early_init_f(void) { init_plls(); k2g_mux_config(); + k2g_reset_mux_config(); + /* deassert FLASH_HOLD */ clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET, BIT(9)); diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 879f25a..68fbf49 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -103,11 +103,11 @@ void pin_mux_usb(void) pinmux_tristate_disable(PMUX_PINGRP_DTE); /* Reset ASIX using LAN_RESET */ - gpio_request(GPIO_PV4, "LAN_RESET"); - gpio_direction_output(GPIO_PV4, 0); + gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET"); + gpio_direction_output(TEGRA_GPIO(V, 4), 0); pinmux_tristate_disable(PMUX_PINGRP_GPV); udelay(5); - gpio_set_value(GPIO_PV4, 1); + gpio_set_value(TEGRA_GPIO(V, 4), 1); /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ pinmux_tristate_disable(PMUX_PINGRP_SPIG); diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 44b5beb..e32362a 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -47,8 +47,8 @@ void pinmux_init(void) void pin_mux_usb(void) { /* Reset ASIX using LAN_RESET */ - gpio_request(GPIO_PDD0, "LAN_RESET"); - gpio_direction_output(GPIO_PDD0, 0); + gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET"); + gpio_direction_output(TEGRA_GPIO(DD, 0), 0); udelay(5); - gpio_set_value(GPIO_PDD0, 1); + gpio_set_value(TEGRA_GPIO(DD, 0), 1); } diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig index 902abf5..67a0228 100644 --- a/board/tplink/wdr4300/Kconfig +++ b/board/tplink/wdr4300/Kconfig @@ -12,4 +12,19 @@ config SYS_BOARD config SYS_CONFIG_NAME default "tplink_wdr4300" +config SYS_TEXT_BASE + default 0xa1000000 + +config SYS_DCACHE_SIZE + default 32768 + +config SYS_DCACHE_LINE_SIZE + default 32 + +config SYS_ICACHE_SIZE + default 65536 + +config SYS_ICACHE_LINE_SIZE + default 32 + endif diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c index bf896fe..d1f3668 100644 --- a/board/xes/common/actl_nand.c +++ b/board/xes/common/actl_nand.c @@ -16,7 +16,7 @@ */ static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); ulong IO_ADDR_W; if (ctrl & NAND_CTRL_CHANGE) { diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig index 461d7dc..02ac65c 100644 --- a/board/xilinx/microblaze-generic/Kconfig +++ b/board/xilinx/microblaze-generic/Kconfig @@ -9,4 +9,28 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "microblaze-generic" +config XILINX_MICROBLAZE0_USE_MSR_INSTR + int "USE_MSR_INSTR range (0:1)" + default 0 + +config XILINX_MICROBLAZE0_USE_PCMP_INSTR + int "USE_PCMP_INSTR range (0:1)" + default 0 + +config XILINX_MICROBLAZE0_USE_BARREL + int "USE_BARREL range (0:1)" + default 0 + +config XILINX_MICROBLAZE0_USE_DIV + int "USE_DIV range (0:1)" + default 0 + +config XILINX_MICROBLAZE0_USE_HW_MUL + int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)" + default 0 + +config XILINX_MICROBLAZE0_HW_VER + string "Core version number" + default 7.10.d + endif diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk index 95ef9c0..1dee2d6 100644 --- a/board/xilinx/microblaze-generic/config.mk +++ b/board/xilinx/microblaze-generic/config.mk @@ -1,16 +1,20 @@ # -# (C) Copyright 2007 Michal Simek +# (C) Copyright 2007 - 2016 Michal Simek # -# Michal SIMEK <monstr@monstr.eu> +# Michal SIMEK <monstr@monstr.eu> # # SPDX-License-Identifier: GPL-2.0+ # -# CAUTION: This file is a faked configuration !!! -# There is no real target for the microblaze-generic -# configuration. You have to replace this file with -# the generated file from your Xilinx design flow. -# -PLATFORM_CPPFLAGS += -mno-xl-soft-mul -PLATFORM_CPPFLAGS += -mno-xl-soft-div -PLATFORM_CPPFLAGS += -mxl-barrel-shift +CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER)) + +# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support. +CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high +CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul +CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div +CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift +CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare + +CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER)) + +PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2) diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index dc5645b..ee7d087 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -14,7 +14,6 @@ #define XILINX_BOARD_NAME microblaze-generic /* Microblaze is microblaze_0 */ -#define XILINX_USE_MSR_INSTR 1 #define XILINX_FSL_NUMBER 3 /* GPIO is LEDs_4Bit*/ diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index eab9303..7de0212 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -7,17 +7,7 @@ obj-y := board.o -# Copied from Xilinx SDK 2014.4 -hw-platform-$(CONFIG_TARGET_ZYNQ_ZED) := zed_hw_platform -hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED) := MicroZed_hw_platform -hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702) := ZC702_hw_platform -hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706) := ZC706_hw_platform -hw-platform-$(CONFIG_TARGET_ZYNQ_ZYBO) := zybo_hw_platform -# If you want to use customized ps7_init_gpl.c/h, -# enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/. -# This line must be placed at the bottom of the list because -# it takes precedence over the default ones. -hw-platform-$(CONFIG_ZYNQ_CUSTOM_INIT) := custom_hw_platform +hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\ $(hw-platform-y)/ps7_init_gpl.o) diff --git a/board/xilinx/zynq/custom_hw_platform/.gitignore b/board/xilinx/zynq/custom_hw_platform/.gitignore deleted file mode 100644 index c455361..0000000 --- a/board/xilinx/zynq/custom_hw_platform/.gitignore +++ /dev/null @@ -1 +0,0 @@ -ps7_init_gpl.[ch] diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c index eb29002..eb29002 100644 --- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h index bdea5a0..bdea5a0 100644 --- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c index abfd911..abfd911 100644 --- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h index 16fa810..16fa810 100644 --- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c index 77fd949..77fd949 100644 --- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h index 8527eef..8527eef 100644 --- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c index f4f45be..f4f45be 100644 --- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h index 9b41e28..9b41e28 100644 --- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c index 83daf7b..83daf7b 100644 --- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h index 22d9fd9..22d9fd9 100644 --- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 2ab3f19..90f00c6 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -1,8 +1,29 @@ # -# (C) Copyright 2014 - 2015 Xilinx, Inc. +# (C) Copyright 2014 - 2016 Xilinx, Inc. # Michal Simek <michal.simek@xilinx.com> # # SPDX-License-Identifier: GPL-2.0+ # obj-y := zynqmp.o + +hw-platform-y :=$(shell echo $(CONFIG_SYS_CONFIG_NAME)) + +init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\ + $(hw-platform-y)/psu_init_gpl.o) + +ifeq ($(init-objs),) +ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),) +init-objs := psu_init_gpl.o +$(if $(CONFIG_SPL_BUILD),\ +$(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/)) +endif +endif + +obj-$(CONFIG_SPL_BUILD) += $(init-objs) + +# Suppress "warning: function declaration isn't a prototype" +CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes + +# To include xil_io.h +CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src) diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h new file mode 100644 index 0000000..57ca4ad --- /dev/null +++ b/board/xilinx/zynqmp/xil_io.h @@ -0,0 +1,35 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H + +/* FIXME remove this when vivado is fixed */ +#include <asm/io.h> + +#define xil_printf(...) + +void Xil_ICacheEnable(void) +{} + +void Xil_DCacheEnable(void) +{} + +void Xil_ICacheDisable(void) +{} + +void Xil_DCacheDisable(void) +{} + +void Xil_Out32(unsigned long addr, unsigned long val) +{ + writel(val, addr); +} + +int Xil_In32(unsigned long addr) +{ + return readl(addr); +} + +#endif /* XIL_IO_H */ diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 132d724..f15dc5d 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -9,12 +9,14 @@ #include <sata.h> #include <ahci.h> #include <scsi.h> +#include <malloc.h> #include <asm/arch/clk.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> #include <usb.h> #include <dwc3-uboot.h> +#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +52,22 @@ int board_early_init_r(void) return 0; } +int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) +{ +#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ + defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \ + defined(CONFIG_ZYNQ_EEPROM_BUS) + i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS); + + if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, + CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, + ethaddr, 6)) + printf("I2C EEPROM MAC address read failed\n"); +#endif + + return 0; +} + #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) /* * fdt_get_reg - Fill buffer by information from DT @@ -197,6 +215,13 @@ int board_late_init(void) { u32 reg = 0; u8 bootmode; + const char *mode; + char *new_targets; + + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { + debug("Saved variables - Skipping\n"); + return 0; + } reg = readl(&crlapb_base->boot_mode); bootmode = reg & BOOT_MODES_MASK; @@ -205,37 +230,49 @@ int board_late_init(void) switch (bootmode) { case JTAG_MODE: puts("JTAG_MODE\n"); - setenv("modeboot", "jtagboot"); + mode = "pxe dhcp"; break; case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: - setenv("modeboot", "qspiboot"); + mode = "qspi0"; puts("QSPI_MODE\n"); break; case EMMC_MODE: puts("EMMC_MODE\n"); - setenv("modeboot", "sdboot"); + mode = "mmc0"; break; case SD_MODE: puts("SD_MODE\n"); - setenv("modeboot", "sdboot"); + mode = "mmc0"; break; case SD_MODE1: puts("SD_MODE1\n"); #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) - setenv("sdbootdev", "1"); + mode = "mmc1"; +#else + mode = "mmc0"; #endif - setenv("modeboot", "sdboot"); break; case NAND_MODE: puts("NAND_MODE\n"); - setenv("modeboot", "nandboot"); + mode = "nand0"; break; default: + mode = ""; printf("Invalid Boot Mode:0x%x\n", bootmode); break; } + /* + * One terminating char + one byte for space between mode + * and default boot_targets + */ + new_targets = calloc(1, strlen(mode) + + strlen(getenv("boot_targets")) + 2); + + sprintf(new_targets, "%s %s", mode, getenv("boot_targets")); + setenv("boot_targets", new_targets); + return 0; } |