ARM: keystone2: use SPD info to configure K2HK and K2E DDR3

This commit replaces hard-coded EMIF and PHY DDR3 configurations for
predefined SODIMMs to a calculated configuration. The SODIMM parameters
are read from SODIMM's SPD and used to calculated the configuration.

The current commit supports calculation for DDR3 with 1600MHz and 1333MHz
only.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

5 files changed, 62 insertions, 260 deletions

diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index d60496e..7ef2d2b 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -1,17 +1,17 @@
 #
 # KS2-EVM: board Makefile
-# (C) Copyright 2012-2014
+# (C) Copyright 2012-2015
 #     Texas Instruments Incorporated, <www.ti.com>
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
 obj-y += board.o
-obj-y += ddr3_cfg.o
 obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
 obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
 obj-$(CONFIG_K2E_EVM) += board_k2e.o
 obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
 obj-$(CONFIG_K2L_EVM) += board_k2l.o
 obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
+obj-$(CONFIG_K2L_EVM) += ddr3_cfg.o
 obj-$(CONFIG_K2G_EVM) += board_k2g.o
 obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o
diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c
index ab44676..b6b59a4 100644
--- a/board/ti/ks2_evm/ddr3_cfg.c
+++ b/board/ti/ks2_evm/ddr3_cfg.c
@@ -9,129 +9,8 @@
 
 #include <common.h>
 
-#include <i2c.h>
 #include <asm/arch/ddr3.h>
-#include <asm/arch/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* DDR3 PHY configuration data with 1600M rate, 8GB size */
-struct ddr3_phy_config ddr3phy_1600_8g = {
-	.pllcr          = 0x0001C000ul,
-	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0           = 0x42C21590ul,
-	.ptr1           = 0xD05612C0ul,
-	.ptr2           = 0, /* not set in gel */
-	.ptr3           = 0x0D861A80ul,
-	.ptr4           = 0x0C827100ul,
-	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
-	.dcr_val        = ((1 << 10)),
-	.dtpr0          = 0xA19DBB66ul,
-	.dtpr1          = 0x32868300ul,
-	.dtpr2          = 0x50035200ul,
-	.mr0            = 0x00001C70ul,
-	.mr1            = 0x00000006ul,
-	.mr2            = 0x00000018ul,
-	.dtcr           = 0x730035C7ul,
-	.pgcr2          = 0x00F07A12ul,
-	.zq0cr1         = 0x0000005Dul,
-	.zq1cr1         = 0x0000005Bul,
-	.zq2cr1         = 0x0000005Bul,
-	.pir_v1         = 0x00000033ul,
-	.pir_v2         = 0x0000FF81ul,
-};
-
-/* DDR3 EMIF configuration data with 1600M rate, 8GB size */
-struct ddr3_emif_config ddr3_1600_8g = {
-	.sdcfg          = 0x6200CE6Aul,
-	.sdtim1         = 0x16709C55ul,
-	.sdtim2         = 0x00001D4Aul,
-	.sdtim3         = 0x435DFF54ul,
-	.sdtim4         = 0x553F0CFFul,
-	.zqcfg          = 0xF0073200ul,
-	.sdrfc          = 0x00001869ul,
-};
-
-#ifdef CONFIG_K2HK_EVM
-/* DDR3 PHY configuration data with 1333M rate, and 2GB size */
-struct ddr3_phy_config ddr3phy_1333_2g = {
-	.pllcr          = 0x0005C000ul,
-	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0           = 0x42C21590ul,
-	.ptr1           = 0xD05612C0ul,
-	.ptr2           = 0, /* not set in gel */
-	.ptr3           = 0x0B4515C2ul,
-	.ptr4           = 0x0A6E08B4ul,
-	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
-	.dcr_val        = ((1 << 10)),
-	.dtpr0          = 0x8558AA55ul,
-	.dtpr1          = 0x32857280ul,
-	.dtpr2          = 0x5002C200ul,
-	.mr0            = 0x00001A60ul,
-	.mr1            = 0x00000006ul,
-	.mr2            = 0x00000010ul,
-	.dtcr           = 0x710035C7ul,
-	.pgcr2          = 0x00F065B8ul,
-	.zq0cr1         = 0x0000005Dul,
-	.zq1cr1         = 0x0000005Bul,
-	.zq2cr1         = 0x0000005Bul,
-	.pir_v1         = 0x00000033ul,
-	.pir_v2         = 0x0000FF81ul,
-};
-
-/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */
-struct ddr3_emif_config ddr3_1333_2g = {
-	.sdcfg          = 0x62008C62ul,
-	.sdtim1         = 0x125C8044ul,
-	.sdtim2         = 0x00001D29ul,
-	.sdtim3         = 0x32CDFF43ul,
-	.sdtim4         = 0x543F0ADFul,
-	.zqcfg          = 0x70073200ul,
-	.sdrfc          = 0x00001457ul,
-};
-#endif
-
-#ifdef CONFIG_K2E_EVM
-/* DDR3 PHY configuration data with 1600M rate, and 4GB size  */
-struct ddr3_phy_config ddr3phy_1600_4g = {
-	.pllcr          = 0x0001C000ul,
-	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
-	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
-	.ptr0           = 0x42C21590ul,
-	.ptr1           = 0xD05612C0ul,
-	.ptr2           = 0, /* not set in gel */
-	.ptr3           = 0x08861A80ul,
-	.ptr4           = 0x0C827100ul,
-	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
-	.dcr_val        = ((1 << 10)),
-	.dtpr0          = 0x9D9CBB66ul,
-	.dtpr1          = 0x12840300ul,
-	.dtpr2          = 0x5002D200ul,
-	.mr0            = 0x00001C70ul,
-	.mr1            = 0x00000006ul,
-	.mr2            = 0x00000018ul,
-	.dtcr           = 0x710035C7ul,
-	.pgcr2          = 0x00F07A12ul,
-	.zq0cr1         = 0x0001005Dul,
-	.zq1cr1         = 0x0001005Bul,
-	.zq2cr1         = 0x0001005Bul,
-	.pir_v1         = 0x00000033ul,
-	.pir_v2         = 0x0000FF81ul,
-};
-
-/* DDR3 EMIF configuration data with 1600M rate, and 4GB size  */
-struct ddr3_emif_config ddr3_1600_4g = {
-	.sdcfg          = 0x6200CE62ul,
-	.sdtim1         = 0x166C9855ul,
-	.sdtim2         = 0x00001D4Aul,
-	.sdtim3         = 0x421DFF53ul,
-	.sdtim4         = 0x543F07FFul,
-	.zqcfg          = 0x70073200ul,
-	.sdrfc          = 0x00001869ul,
-};
-#endif
+#include "ddr3_cfg.h"
 
 struct ddr3_phy_config ddr3phy_1600_2g = {
 	.pllcr          = 0x0001C000ul,
@@ -168,39 +47,3 @@ struct ddr3_emif_config ddr3_1600_2g = {
 	.zqcfg          = 0x70073200ul,
 	.sdrfc          = 0x00001869ul,
 };
-
-int ddr3_get_dimm_params(char *dimm_name)
-{
-	int ret;
-	int old_bus;
-	u8 spd_params[256];
-
-	i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
-
-	old_bus = i2c_get_bus_num();
-	i2c_set_bus_num(1);
-
-	ret = i2c_read(0x53, 0, 1, spd_params, 256);
-
-	i2c_set_bus_num(old_bus);
-
-	dimm_name[0] = '\0';
-
-	if (ret) {
-		puts("Cannot read DIMM params\n");
-		return 1;
-	}
-
-	/*
-	 * We need to convert spd data to dimm parameters
-	 * and to DDR3 EMIF and PHY regirsters values.
-	 * For now we just return DIMM type string value.
-	 * Caller may use this value to choose appropriate
-	 * a pre-set DDR3 configuration
-	 */
-
-	strncpy(dimm_name, (char *)&spd_params[0x80], 18);
-	dimm_name[18] = '\0';
-
-	return 0;
-}
diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h
index 5bd786c..f95edde 100644
--- a/board/ti/ks2_evm/ddr3_cfg.h
+++ b/board/ti/ks2_evm/ddr3_cfg.h
@@ -10,18 +10,11 @@
 #ifndef __DDR3_CFG_H
 #define __DDR3_CFG_H
 
-extern struct ddr3_phy_config ddr3phy_1600_8g;
-extern struct ddr3_emif_config ddr3_1600_8g;
-
-extern struct ddr3_phy_config ddr3phy_1333_2g;
-extern struct ddr3_emif_config ddr3_1333_2g;
-
-extern struct ddr3_phy_config ddr3phy_1600_4g;
-extern struct ddr3_emif_config ddr3_1600_4g;
+#include <asm/arch/ddr3.h>
 
 extern struct ddr3_phy_config ddr3phy_1600_2g;
 extern struct ddr3_emif_config ddr3_1600_2g;
 
-int ddr3_get_dimm_params(char *dimm_name);
+int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb);
 
 #endif /* __DDR3_CFG_H */
diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c
index 35ffb42..e82aa66 100644
--- a/board/ti/ks2_evm/ddr3_k2e.c
+++ b/board/ti/ks2_evm/ddr3_k2e.c
@@ -1,7 +1,7 @@
 /*
  * Keystone2: DDR3 initialization
  *
- * (C) Copyright 2014
+ * (C) Copyright 2014-2015
  *     Texas Instruments Incorporated, <www.ti.com>
  *
  * SPDX-License-Identifier:     GPL-2.0+
@@ -12,42 +12,37 @@
 #include <asm/arch/ddr3.h>
 
 static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+static struct pll_init_data ddr3_333 = DDR3_PLL_333;
 
 u32 ddr3_init(void)
 {
-	u32 ddr3_size;
-	char dimm_name[32];
+	struct ddr3_spd_cb spd_cb;
 
-	if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
-		init_pll(&ddr3_400);
+	if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
+		printf("Sorry, I don't know how to configure DDR3A.\n"
+		       "Bye :(\n");
+		for (;;)
+			;
+	}
 
-	ddr3_get_dimm_params(dimm_name);
+	printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
 
-	printf("Detected SO-DIMM [%s]\n", dimm_name);
+	printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
+	if (spd_cb.ddrspdclock == 1600)
+		init_pll(&ddr3_400);
+	else
+		init_pll(&ddr3_333);
 
 	/* Reset DDR3 PHY after PLL enabled */
 	ddr3_reset_ddrphy();
 
-	if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
-		/* 8G SO-DIMM */
-		ddr3_size = 8;
-		printf("DRAM: 8 GiB\n");
-		ddr3phy_1600_8g.zq0cr1 |= 0x10000;
-		ddr3phy_1600_8g.zq1cr1 |= 0x10000;
-		ddr3phy_1600_8g.zq2cr1 |= 0x10000;
-		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
-		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g);
-	} else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) {
-		/* 4G SO-DIMM */
-		ddr3_size = 4;
-		printf("DRAM: 4 GiB\n");
-		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
-		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
-	} else {
-		printf("Unknown SO-DIMM. Cannot configure DDR3\n");
-		while (1)
-			;
-	}
+	spd_cb.phy_cfg.zq0cr1 |= 0x10000;
+	spd_cb.phy_cfg.zq1cr1 |= 0x10000;
+	spd_cb.phy_cfg.zq2cr1 |= 0x10000;
+	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
+	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
+
+	printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte);
 
-	return ddr3_size;
+	return (u32)spd_cb.ddr_size_gbyte;
 }
diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c
index b36eb27..f848422 100644
--- a/board/ti/ks2_evm/ddr3_k2hk.c
+++ b/board/ti/ks2_evm/ddr3_k2hk.c
@@ -17,77 +17,48 @@ struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
 
 u32 ddr3_init(void)
 {
-	char dimm_name[32];
 	u32 ddr3_size;
+	struct ddr3_spd_cb spd_cb;
 
-	ddr3_get_dimm_params(dimm_name);
+	if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
+		printf("Sorry, I don't know how to configure DDR3A.\n"
+		       "Bye :(\n");
+		for (;;)
+			;
+	}
 
-	printf("Detected SO-DIMM [%s]\n", dimm_name);
+	printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
 
-	if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
-		init_pll(&ddr3a_400);
-		if (cpu_revision() > 0) {
-			if (cpu_revision() > 1) {
-				/* PG 2.0 */
-				/* Reset DDR3A PHY after PLL enabled */
-				ddr3_reset_ddrphy();
-				ddr3phy_1600_8g.zq0cr1 |= 0x10000;
-				ddr3phy_1600_8g.zq1cr1 |= 0x10000;
-				ddr3phy_1600_8g.zq2cr1 |= 0x10000;
-				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-						 &ddr3phy_1600_8g);
-			} else {
-				/* PG 1.1 */
-				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-						 &ddr3phy_1600_8g);
-			}
+	if ((cpu_revision() > 1) ||
+	    (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) {
+		printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
+		if (spd_cb.ddrspdclock == 1600)
+			init_pll(&ddr3a_400);
+		else
+			init_pll(&ddr3a_333);
+	}
 
-			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-					  &ddr3_1600_8g);
-			printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
-			ddr3_size = 8;
-		} else {
-			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
-			ddr3_1600_8g.sdcfg |= 0x1000;
-			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-					  &ddr3_1600_8g);
-			printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
-			ddr3_size = 4;
-		}
-	} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
-		init_pll(&ddr3a_333);
-		if (cpu_revision() > 0) {
-			if (cpu_revision() > 1) {
-				/* PG 2.0 */
-				/* Reset DDR3A PHY after PLL enabled */
-				ddr3_reset_ddrphy();
-				ddr3phy_1333_2g.zq0cr1 |= 0x10000;
-				ddr3phy_1333_2g.zq1cr1 |= 0x10000;
-				ddr3phy_1333_2g.zq2cr1 |= 0x10000;
-				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-						 &ddr3phy_1333_2g);
-			} else {
-				/* PG 1.1 */
-				ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-						 &ddr3phy_1333_2g);
-			}
-			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-					  &ddr3_1333_2g);
-			ddr3_size = 2;
-			printf("DRAM:  2 GiB");
-		} else {
-			ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
-			ddr3_1333_2g.sdcfg |= 0x1000;
-			ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-					  &ddr3_1333_2g);
-			ddr3_size = 1;
-			printf("DRAM:  1 GiB");
+	if (cpu_revision() > 0) {
+		if (cpu_revision() > 1) {
+			/* PG 2.0 */
+			/* Reset DDR3A PHY after PLL enabled */
+			ddr3_reset_ddrphy();
+			spd_cb.phy_cfg.zq0cr1 |= 0x10000;
+			spd_cb.phy_cfg.zq1cr1 |= 0x10000;
+			spd_cb.phy_cfg.zq2cr1 |= 0x10000;
 		}
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
+
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
+
+		ddr3_size = spd_cb.ddr_size_gbyte;
 	} else {
-		printf("Unknown SO-DIMM. Cannot configure DDR3\n");
-		while (1)
-			;
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
+		spd_cb.emif_cfg.sdcfg |= 0x1000;
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
+		ddr3_size = spd_cb.ddr_size_gbyte / 2;
 	}
+	printf("DRAM: %d GiB (includes reported below)\n", ddr3_size);
 
 	/* Apply the workaround for PG 1.0 and 1.1 Silicons */
 	if (cpu_revision() <= 1)