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| author | Michal Simek <michal.simek@xilinx.com> | 2013-04-22 15:43:02 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-05-06 10:41:24 +0200 |
| commit | d5dae85f23c7c902731512e451afde9a6e4a250a (patch) | |
| tree | 8b7230045d9b0c43400e2ed661fb9282c662472c /board | |
| parent | 5bd0bd7cef396a830996b4ad91b89b7d205c7298 (diff) | |
| download | u-boot-imx-d5dae85f23c7c902731512e451afde9a6e4a250a.zip u-boot-imx-d5dae85f23c7c902731512e451afde9a6e4a250a.tar.gz u-boot-imx-d5dae85f23c7c902731512e451afde9a6e4a250a.tar.bz2 | |
fpga: zynq: Add support for loading bitstream
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.
The first driver version was done by:
Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/xilinx/zynq/board.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 1589d21..b02c364 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -22,15 +22,52 @@ #include <common.h> #include <netdev.h> +#include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_FPGA +Xilinx_desc fpga; + +/* It can be done differently */ +Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); +Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); +Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +#endif + int board_init(void) { +#ifdef CONFIG_FPGA + u32 idcode; + + idcode = zynq_slcr_get_idcode(); + + switch (idcode) { + case XILINX_ZYNQ_7010: + fpga = fpga010; + break; + case XILINX_ZYNQ_7020: + fpga = fpga020; + break; + case XILINX_ZYNQ_7030: + fpga = fpga030; + break; + case XILINX_ZYNQ_7045: + fpga = fpga045; + break; + } +#endif + icache_enable(); +#ifdef CONFIG_FPGA + fpga_init(); + fpga_add(fpga_xilinx, &fpga); +#endif + return 0; } |