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authorMichael Kurz <michi.kurz@gmail.com>2017-01-22 16:04:30 +0100
committerTom Rini <trini@konsulko.com>2017-01-28 14:04:50 -0500
commitd4363baada1505e126fc75c292f17903ab9c9e3a (patch)
tree4098bb4df9a609c359ac687d470473a29b4d3545 /board
parentfc0d3dbc6e5e841309611bf900adc88c7d439b47 (diff)
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ARM: SPI: stm32: add stm32f746 qspi driver
This patch adds support for the QSPI IP found in stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
Diffstat (limited to 'board')
-rw-r--r--board/st/stm32f746-disco/stm32f746-disco.c60
1 files changed, 60 insertions, 0 deletions
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 6c16138..7ed7bf7 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -326,6 +326,60 @@ static int stmmac_setup(void)
}
#endif
+#ifdef CONFIG_STM32_QSPI
+const struct stm32_gpio_ctl gpio_ctl_qspi_9 = {
+ .mode = STM32_GPIO_MODE_AF,
+ .otype = STM32_GPIO_OTYPE_PP,
+ .speed = STM32_GPIO_SPEED_100M,
+ .pupd = STM32_GPIO_PUPD_NO,
+ .af = STM32_GPIO_AF9
+};
+
+const struct stm32_gpio_ctl gpio_ctl_qspi_10 = {
+ .mode = STM32_GPIO_MODE_AF,
+ .otype = STM32_GPIO_OTYPE_PP,
+ .speed = STM32_GPIO_SPEED_100M,
+ .pupd = STM32_GPIO_PUPD_NO,
+ .af = STM32_GPIO_AF10
+};
+
+static const struct stm32_gpio_dsc qspi_af9_gpio[] = {
+ {STM32_GPIO_PORT_B, STM32_GPIO_PIN_2}, /* QUADSPI_CLK */
+ {STM32_GPIO_PORT_D, STM32_GPIO_PIN_11}, /* QUADSPI_BK1_IO0 */
+ {STM32_GPIO_PORT_D, STM32_GPIO_PIN_12}, /* QUADSPI_BK1_IO1 */
+ {STM32_GPIO_PORT_D, STM32_GPIO_PIN_13}, /* QUADSPI_BK1_IO3 */
+ {STM32_GPIO_PORT_E, STM32_GPIO_PIN_2}, /* QUADSPI_BK1_IO2 */
+};
+
+static const struct stm32_gpio_dsc qspi_af10_gpio[] = {
+ {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* QUADSPI_BK1_NCS */
+};
+
+static int qspi_setup(void)
+{
+ int res = 0;
+ int i;
+
+ clock_setup(GPIO_B_CLOCK_CFG);
+ clock_setup(GPIO_D_CLOCK_CFG);
+ clock_setup(GPIO_E_CLOCK_CFG);
+
+ for (i = 0; i < ARRAY_SIZE(qspi_af9_gpio); i++) {
+ res = stm32_gpio_config(&qspi_af9_gpio[i], &gpio_ctl_qspi_9);
+ if (res)
+ return res;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(qspi_af10_gpio); i++) {
+ res = stm32_gpio_config(&qspi_af10_gpio[i], &gpio_ctl_qspi_10);
+ if (res)
+ return res;
+ }
+
+ return 0;
+}
+#endif
+
u32 get_board_rev(void)
{
return 0;
@@ -346,6 +400,12 @@ int board_early_init_f(void)
return res;
#endif
+#ifdef CONFIG_STM32_QSPI
+ res = qspi_setup();
+ if (res)
+ return res;
+#endif
+
return 0;
}