MLK-13450-19 imx: mx7ulp_evk: Add EVK boards support codes

Add basic support for i.MX7ULP EVK board.
I2C, SD/eMMC, UART, QSPI and USB are added.

Use target mx7ulp_evk_config to select the configuration.
Use mx7ulp_evk_emmc_config for eMMC boot.
Use mx7ulp_evk_m4boot_config for binding and booting m4 image in
single boot mode.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>

4 files changed, 435 insertions, 0 deletions

diff --git a/board/freescale/mx7ulp_evk/Kconfig b/board/freescale/mx7ulp_evk/Kconfig
new file mode 100644
index 0000000..ff44831
--- /dev/null
+++ b/board/freescale/mx7ulp_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX7ULP_EVK
+
+config SYS_BOARD
+	default "mx7ulp_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx7ulp_evk"
+
+endif
diff --git a/board/freescale/mx7ulp_evk/Makefile b/board/freescale/mx7ulp_evk/Makefile
new file mode 100644
index 0000000..c92c21e
--- /dev/null
+++ b/board/freescale/mx7ulp_evk/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx7ulp_evk.o
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg
new file mode 100644
index 0000000..ce85e50
--- /dev/null
+++ b/board/freescale/mx7ulp_evk/imximage.cfg
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+/*PLUGIN	board/freescale/mx7ulp_evk/plugin.bin 0x00910000*/
+#error  "PLUGIN not supported yet"
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00dc 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e0508 0x00140000
+DATA 4   0x403E0510 0x00000004
+DATA 4   0x403E0514 0x00000002
+DATA 4   0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+DATA 4   0x403e050c 0x8080801E
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00dc 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x00000180
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0890 0x00400000
+
+DATA 4   0x40AB0848 0x40404040
+DATA 4   0x40AB0850 0x40404040
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+
+DATA 4   0x40AB082C 0xf3333333
+DATA 4   0x40AB0830 0xf3333333
+DATA 4   0x40AB0834 0xf3333333
+DATA 4   0x40AB0838 0xf3333333
+
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB08B8 0x00000800
+
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB000C 0x292C42F3
+DATA 4   0x40AB0010 0x00100A22
+DATA 4   0x40AB0038 0x00120556
+DATA 4   0x40AB0014 0x00C700DB
+DATA 4   0x40AB0018 0x00211718
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0040 0x0000003F
+DATA 4   0x40AB0000 0xC3190000
+DATA 4   0x40AB083C 0x20000000
+
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0x003F8038
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0xFF0A8038
+DATA 4   0x40AB001C 0x04028030
+DATA 4   0x40AB001C 0x04028038
+DATA 4   0x40AB001C 0x83018030
+DATA 4   0x40AB001C 0x83018038
+DATA 4   0x40AB001C 0x01038030
+DATA 4   0x40AB001C 0x01038038
+
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1310000
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB0404 0x00011006
+DATA 4   0x40AB001C 0x00000000
+
+#endif
diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c
new file mode 100644
index 0000000..2939915
--- /dev/null
+++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx7ulp-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_UP | PAD_CTL_DSE)
+#define ESDHC_CD_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_PUS_UP)
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_UP)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_UP | PAD_CTL_ODE)
+
+#define GPIO_PAD_CTRL	(PAD_CTL_OBE_ENABLE | PAD_CTL_IBE_ENABLE)
+
+#define QSPI_PAD_CTRL1	(PAD_CTL_PUS_UP | PAD_CTL_DSE)
+
+#define QSPI_PAD_CTRL0	(PAD_CTL_PUS_UP | PAD_CTL_DSE \
+	| PAD_CTL_OBE_ENABLE)
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static int mx7ulp_board_rev(void)
+{
+	return 0x41;
+}
+
+u32 get_board_rev(void)
+{
+	int rev = mx7ulp_board_rev();
+
+	return (get_cpu_rev() & ~(0xF << 8)) | rev;
+}
+
+static iomux_cfg_t const lpuart4_pads[] = {
+	MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, ARRAY_SIZE(lpuart4_pads));
+}
+
+#ifdef CONFIG_SYS_I2C_IMX
+static iomux_cfg_t const i2c5_pads[] = {
+	MX7ULP_PAD_PTC4__LPI2C5_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	MX7ULP_PAD_PTC5__LPI2C5_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+};
+
+static iomux_cfg_t const i2c7_pads[] = {
+	MX7ULP_PAD_PTF12__LPI2C7_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	MX7ULP_PAD_PTF13__LPI2C7_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+};
+
+void i2c_init_board(void)
+{
+	mx7ulp_iomux_setup_multiple_pads(i2c5_pads, ARRAY_SIZE(i2c5_pads));
+	mx7ulp_iomux_setup_multiple_pads(i2c7_pads, ARRAY_SIZE(i2c7_pads));
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX7
+/*Need rework for ID and PWR_EN pins*/
+static iomux_cfg_t const usb_otg1_pads[] = {
+	MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(GPIO_PAD_CTRL),  /* gpio for power en */
+	MX7ULP_PAD_PTC8__PTC8 | MUX_PAD_CTRL(GPIO_PAD_CTRL),  /* gpio for OTG ID*/
+};
+
+static void setup_usb(void)
+{
+	mx7ulp_iomux_setup_multiple_pads(usb_otg1_pads,
+						 ARRAY_SIZE(usb_otg1_pads));
+
+	gpio_request(IMX_GPIO_NR(3, 8), "otg_id");
+	gpio_direction_input(IMX_GPIO_NR(3, 8));
+
+	gpio_request(IMX_GPIO_NR(3, 0), "otg_pwr");
+}
+
+/*Needs to override the ehci power if controlled by GPIO */
+int board_ehci_power(int port, int on)
+{
+	switch (port) {
+	case 0:
+		if (on)
+			gpio_direction_output(IMX_GPIO_NR(3, 0), 1);
+		else
+			gpio_direction_output(IMX_GPIO_NR(3, 0), 0);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int board_usb_phy_mode(int port)
+{
+	int ret = 0;
+
+	if (port == 0) {
+		ret = gpio_get_value(IMX_GPIO_NR(3, 8));
+
+		if (ret)
+			return USB_INIT_DEVICE;
+		else
+			return USB_INIT_HOST;
+	}
+
+	return USB_INIT_HOST;
+}
+
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_QSPI
+static iomux_cfg_t const quadspi_pads[] = {
+	MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB15__QSPIA_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+	u32 val;
+
+	mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
+
+	/* enable clock */
+	val = readl(PCC1_RBASE + 0x94);
+
+	if (!(val & 0x20000000)) {
+		writel(0x03000003, (PCC1_RBASE + 0x94));
+		writel(0x43000003, (PCC1_RBASE + 0x94));
+	}
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_USB_EHCI_MX7
+	setup_usb();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC0_RBASE, 0, 4},
+};
+
+static iomux_cfg_t const usdhc0_pads[] = {
+	MX7ULP_PAD_PTD0__SDHC0_RESET_b | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	MX7ULP_PAD_PTD1__SDHC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	MX7ULP_PAD_PTD2__SDHC0_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	MX7ULP_PAD_PTD7__SDHC0_D3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	MX7ULP_PAD_PTD8__SDHC0_D2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	MX7ULP_PAD_PTD9__SDHC0_D1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	MX7ULP_PAD_PTD10__SDHC0_D0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+
+#ifdef CONFIG_MX7ULP_EVK_EMMC
+	MX7ULP_PAD_PTD11__SDHC0_DQS | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+#else
+	/* CD */
+	MX7ULP_PAD_PTC10__PTC10 | MUX_PAD_CTRL(ESDHC_CD_GPIO_PAD_CTRL),
+#endif
+};
+
+#define USDHC0_CD_GPIO	IMX_GPIO_NR(3, 10)
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC0
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			mx7ulp_iomux_setup_multiple_pads(usdhc0_pads, ARRAY_SIZE(usdhc0_pads));
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+#ifndef CONFIG_MX7ULP_EVK_EMMC
+			gpio_request(USDHC0_CD_GPIO, "usdhc0_cd");
+			gpio_direction_input(USDHC0_CD_GPIO);
+#endif
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+			}
+
+			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+			if (ret)
+				return ret;
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC0_RBASE:
+#ifdef CONFIG_MX7ULP_EVK_EMMC
+		ret = 1;
+#else
+		ret = !gpio_get_value(USDHC0_CD_GPIO);
+#endif
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+#endif
+
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: i.MX7ULP EVK board\n");
+
+	return 0;
+}