Merge branch 'u-boot/master'

59 files changed, 930 insertions, 308 deletions

diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h
index 39afbba..e4896fb 100644
--- a/board/BuR/common/bur_common.h
+++ b/board/BuR/common/bur_common.h
@@ -16,10 +16,9 @@
 
 int load_lcdtiming(struct am335x_lcdpanel *panel);
 void br_summaryscreen(void);
-void blink(u32 blinks, u32 intervall, u32 pin);
 void pmicsetup(u32 mpupll);
 void enable_uart0_pin_mux(void);
-void enable_i2c0_pin_mux(void);
+void enable_i2c_pin_mux(void);
 void enable_board_pin_mux(void);
 int board_eth_init(bd_t *bis);
 
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index 5ff8a7e..ccaa9c6 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -441,30 +441,12 @@ void lcd_enable(void)
 #error "LCD-support with a suitable FB-Driver is mandatory !"
 #endif /* CONFIG_LCD */
 
-void blink(u32 blinks, u32 intervall, u32 pin)
-{
-	gpio_direction_output(pin, 0);
-	int val = 0;
-
-	do {
-		val ^= 0x01;
-		gpio_set_value(pin, val);
-		mdelay(intervall);
-	} while (blinks--);
-
-	gpio_set_value(pin, 0);
-}
-
 #ifdef CONFIG_SPL_BUILD
 void pmicsetup(u32 mpupll)
 {
 	int mpu_vdd;
 	int usb_cur_lim;
 
-	/* setup I2C */
-	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
 	if (i2c_probe(TPS65217_CHIP_PM)) {
 		puts("PMIC (0x24) not found! skip further initalization.\n");
 		return;
diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c
index 892311e..6eed7e0 100644
--- a/board/BuR/kwb/board.c
+++ b/board/BuR/kwb/board.c
@@ -124,7 +124,8 @@ void am33xx_spl_board_init(void)
 	gpio_direction_output(LCD_PWR, 0);
 
 	/* setup I2C */
-	enable_i2c0_pin_mux();
+	enable_i2c_pin_mux();
+	i2c_set_bus_num(0);
 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 
 	/* power-ON  3V3 via Resetcontroller */
diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c
index 9f89b5e..2b1d8d3 100644
--- a/board/BuR/kwb/mux.c
+++ b/board/BuR/kwb/mux.c
@@ -180,7 +180,7 @@ void enable_uart0_pin_mux(void)
 	configure_module_pin_mux(uart0_pin_mux);
 }
 
-void enable_i2c0_pin_mux(void)
+void enable_i2c_pin_mux(void)
 {
 	configure_module_pin_mux(i2c0_pin_mux);
 }
diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c
index 9402aa4..89e989f 100644
--- a/board/BuR/tseries/board.c
+++ b/board/BuR/tseries/board.c
@@ -123,6 +123,10 @@ void am33xx_spl_board_init(void)
 	/* setup LCD-Pixel Clock */
 	writel(0x2, &cmdpll->clklcdcpixelclk);	/* clock comes from perPLL M2 */
 
+	/* setup I2C */
+	enable_i2c_pin_mux();
+	i2c_set_bus_num(0);
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 	pmicsetup(0);
 }
 
diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c
index 2c87a63..ac7e885 100644
--- a/board/BuR/tseries/mux.c
+++ b/board/BuR/tseries/mux.c
@@ -226,7 +226,7 @@ void enable_uart0_pin_mux(void)
 	configure_module_pin_mux(uart0_pin_mux);
 }
 
-void enable_i2c0_pin_mux(void)
+void enable_i2c_pin_mux(void)
 {
 	configure_module_pin_mux(i2c0_pin_mux);
 }
diff --git a/board/amcc/acadia/Kconfig b/board/amcc/acadia/Kconfig
index 033deaf..7c0ef53 100644
--- a/board/amcc/acadia/Kconfig
+++ b/board/amcc/acadia/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "acadia"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/bamboo/Kconfig b/board/amcc/bamboo/Kconfig
index c0bd40a..d44a36a 100644
--- a/board/amcc/bamboo/Kconfig
+++ b/board/amcc/bamboo/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "bamboo"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/bubinga/Kconfig b/board/amcc/bubinga/Kconfig
index 540d9b6..fc40f6e 100644
--- a/board/amcc/bubinga/Kconfig
+++ b/board/amcc/bubinga/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "bubinga"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig
index 848e08f..46efa7a 100644
--- a/board/amcc/canyonlands/Kconfig
+++ b/board/amcc/canyonlands/Kconfig
@@ -39,12 +39,4 @@ config DM
 config DM_SERIAL
 	default y
 
-config SYS_MALLOC_F
-	bool
-	default y
-
-config SYS_MALLOC_F_LEN
-	hex
-	default 0x400
-
 endif
diff --git a/board/amcc/ebony/Kconfig b/board/amcc/ebony/Kconfig
index 62394b6..ba73148 100644
--- a/board/amcc/ebony/Kconfig
+++ b/board/amcc/ebony/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "ebony"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/katmai/Kconfig b/board/amcc/katmai/Kconfig
index fc606cf..59d3ef5 100644
--- a/board/amcc/katmai/Kconfig
+++ b/board/amcc/katmai/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "katmai"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/kilauea/Kconfig b/board/amcc/kilauea/Kconfig
index 3f2f434..5dfd9eb 100644
--- a/board/amcc/kilauea/Kconfig
+++ b/board/amcc/kilauea/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "kilauea"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/luan/Kconfig b/board/amcc/luan/Kconfig
index 3df90af..36b44ff 100644
--- a/board/amcc/luan/Kconfig
+++ b/board/amcc/luan/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "luan"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/makalu/Kconfig b/board/amcc/makalu/Kconfig
index 31ce5f1..7f8498a 100644
--- a/board/amcc/makalu/Kconfig
+++ b/board/amcc/makalu/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "makalu"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/ocotea/Kconfig b/board/amcc/ocotea/Kconfig
index 18c1a15..489e8a4 100644
--- a/board/amcc/ocotea/Kconfig
+++ b/board/amcc/ocotea/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "ocotea"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/redwood/Kconfig b/board/amcc/redwood/Kconfig
index d710590..fee6441 100644
--- a/board/amcc/redwood/Kconfig
+++ b/board/amcc/redwood/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "redwood"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/sequoia/Kconfig b/board/amcc/sequoia/Kconfig
index 67ee3ca..6e6e408 100644
--- a/board/amcc/sequoia/Kconfig
+++ b/board/amcc/sequoia/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "sequoia"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/taihu/Kconfig b/board/amcc/taihu/Kconfig
index fc5cb1d..faafb08 100644
--- a/board/amcc/taihu/Kconfig
+++ b/board/amcc/taihu/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "taihu"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/taishan/Kconfig b/board/amcc/taishan/Kconfig
index abd07f5..9ad8a4c 100644
--- a/board/amcc/taishan/Kconfig
+++ b/board/amcc/taishan/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "taishan"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/walnut/Kconfig b/board/amcc/walnut/Kconfig
index 94e3dc9..d4c451d 100644
--- a/board/amcc/walnut/Kconfig
+++ b/board/amcc/walnut/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "walnut"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/yosemite/Kconfig b/board/amcc/yosemite/Kconfig
index dfa1068..ec51236 100644
--- a/board/amcc/yosemite/Kconfig
+++ b/board/amcc/yosemite/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "yosemite"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/amcc/yucca/Kconfig b/board/amcc/yucca/Kconfig
index 61d9589..338b6a9 100644
--- a/board/amcc/yucca/Kconfig
+++ b/board/amcc/yucca/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "yucca"
 
+config DISPLAY_BOARDINFO
+	bool
+	default y
+
 endif
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index 7d5e7be..f5693ae 100644
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -1,16 +1,3 @@
-if TARGET_VEXPRESS64_AEMV8A
-
-config SYS_BOARD
-	default "vexpress64"
-
-config SYS_VENDOR
-	default "armltd"
-
-config SYS_CONFIG_NAME
-	default "vexpress_aemv8a"
-
-endif
-
 if TARGET_VEXPRESS64_BASE_FVP
 
 config SYS_BOARD
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 071d88c..13dd667 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -11,7 +11,6 @@
 #include <netdev.h>
 #include <asm/io.h>
 #include <linux/compiler.h>
-#include <asm/semihosting.h>
 #include <dm/platdata.h>
 #include <dm/platform_data/serial_pl01x.h>
 
@@ -46,101 +45,6 @@ void reset_cpu(ulong addr)
 {
 }
 
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_SEMIHOSTING
-	/*
-	 * Please refer to doc/README.semihosting for a more complete
-	 * description.
-	 *
-	 * We require that the board include file defines these env variables:
-	 * - kernel_name
-	 * - kernel_addr_r
-	 * - initrd_name
-	 * - initrd_addr_r
-	 * - fdt_name
-	 * - fdt_addr_r
-	 *
-	 * For the "fdt chosen" startup macro, this code will then define:
-	 * - initrd_end (based on initrd_addr_r plus actual initrd_size)
-	 *
-	 * We will then load the kernel, initrd, and fdt into the specified
-	 * locations in memory in a similar way that the ATF fastmodel code
-	 * uses semihosting calls to load other boot stages and u-boot itself.
-	 */
-
-	/* Env variable strings */
-	char *kernel_name = getenv("kernel_name");
-	char *kernel_addr_str = getenv("kernel_addr_r");
-	char *initrd_name = getenv("initrd_name");
-	char *initrd_addr_str = getenv("initrd_addr_r");
-	char *fdt_name = getenv("fdt_name");
-	char *fdt_addr_str = getenv("fdt_addr_r");
-	char initrd_end_str[64];
-
-	/* Actual addresses converted from env variables */
-	void *kernel_addr_r;
-	void *initrd_addr_r;
-	void *fdt_addr_r;
-
-	/* Actual initrd base and size */
-	unsigned long initrd_base;
-	unsigned long initrd_size;
-
-	/* Space available */
-	int avail;
-
-	/* Make sure the environment variables needed are set */
-	if (!(kernel_addr_str && initrd_addr_str && fdt_addr_str)) {
-		printf("%s: Define {kernel/initrd/fdt}_addr_r\n", __func__);
-		return -1;
-	}
-	if (!(kernel_name && initrd_name && fdt_name)) {
-		printf("%s: Define {kernel/initrd/fdt}_name\n", __func__);
-		return -1;
-	}
-
-	/* Get exact initrd_size */
-	initrd_size = smh_len(initrd_name);
-	if (initrd_size == -1) {
-		printf("%s: Can't get file size for \'%s\'\n", __func__,
-		       initrd_name);
-		return -1;
-	}
-
-	/* Set initrd_end */
-	initrd_base = simple_strtoul(initrd_addr_str, NULL, 16);
-	initrd_addr_r = (void *)initrd_base;
-	sprintf(initrd_end_str, "0x%lx", initrd_base + initrd_size - 1);
-	setenv("initrd_end", initrd_end_str);
-
-	/* Load kernel to memory */
-	fdt_addr_r = (void *)simple_strtoul(fdt_addr_str, NULL, 16);
-	kernel_addr_r = (void *)simple_strtoul(kernel_addr_str, NULL, 16);
-
-	/*
-	 * The kernel must be lower in memory than fdt and loading the
-	 * kernel must not trample the fdt or vice versa.
-	 */
-	avail = fdt_addr_r - kernel_addr_r;
-	if (avail < 0) {
-		printf("%s: fdt must be after kernel\n", __func__);
-		return -1;
-	}
-	smh_load(kernel_name, kernel_addr_r, avail, 1);
-
-	/* Load fdt to memory */
-	smh_load(fdt_name, fdt_addr_r, 0x20000, 1);
-
-	/* Load initrd to memory */
-	smh_load(initrd_name, initrd_addr_r, initrd_size, 1);
-
-#endif				/* CONFIG_SEMIHOSTING */
-	return 0;
-}
-#endif				/* CONFIG_BOARD_LATE_INIT */
-
 /*
  * Board specific ethernet initialization routine.
  */
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index b807ef9..4289179 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/at91sam9g45_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
@@ -15,6 +16,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
 #include <lcd.h>
+#include <linux/mtd/nand.h>
 #include <atmel_lcdc.h>
 #include <atmel_mci.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -71,6 +73,84 @@ void at91sam9m10g45ek_nand_hw_init(void)
 }
 #endif
 
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+	/*
+	 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
+	 * test mode, so it needs do some action to exit test mode.
+	 */
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+	at91_set_gpio_output(AT91_PIN_PD7, 0);
+	at91_set_gpio_output(AT91_PIN_PD8, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
+
+#ifdef CONFIG_SYS_USE_MMC
+	at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	at91sam9m10g45ek_nand_hw_init();
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_DQMS_SHARED |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+
+	ddr2->rtr = 0x24b;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddr ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* enable DDR2 clock */
+	writel(0x4, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&mat->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
+	writel(csa, &mat->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_CS6, &ddr2);
+}
+#endif
+
 #ifdef CONFIG_CMD_USB
 static void at91sam9m10g45ek_usb_hw_init(void)
 {
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index 9adc992..4f46a03 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -257,3 +257,76 @@ int dram_init(void)
 					CONFIG_SYS_SDRAM_SIZE);
 	return 0;
 }
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	at91sam9n12ek_nand_hw_init();
+#elif CONFIG_SYS_USE_SPIFLASH
+	at91_spi0_hw_init(1 << 4);
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_13 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddr ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* enable DDR2 clock */
+	writel(0x4, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+	csa |= AT91_MATRIX_EBI_DBPD_OFF;
+	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+	writel(csa, &matrix->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_CS1, &ddr2);
+}
+#endif
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 17a2a40..114ac5c 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -293,3 +293,77 @@ int dram_init(void)
 					CONFIG_SYS_SDRAM_SIZE);
 	return 0;
 }
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	at91sam9x5ek_nand_hw_init();
+#elif CONFIG_SYS_USE_SPIFLASH
+	at91_spi0_hw_init(1 << 4);
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_13 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddr ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* enable DDR2 clock */
+	writel(0x4, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+	csa |= AT91_MATRIX_EBI_DBPD_OFF;
+	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+	writel(csa, &matrix->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_CS1, &ddr2);
+}
+#endif
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index e7f225a..7d447fe 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -24,6 +24,7 @@
 #include <netdev.h>
 #include <nand.h>
 #include <spi.h>
+#include <version.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -179,6 +180,7 @@ void lcd_show_board_info(void)
 	int i;
 	char temp[32];
 
+	lcd_printf("%s\n", U_BOOT_VERSION);
 	lcd_printf("2014 ATMEL Corp\n");
 	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
 		   strmhz(temp, get_cpu_clk_rate()));
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index 46e5041..e9bbb4b 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -24,6 +24,7 @@
 #include <netdev.h>
 #include <nand.h>
 #include <spi.h>
+#include <version.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -174,6 +175,7 @@ void lcd_show_board_info(void)
 	int i;
 	char temp[32];
 
+	lcd_printf("%s\n", U_BOOT_VERSION);
 	lcd_printf("2014 ATMEL Corp\n");
 	lcd_printf("at91@atmel.com\n");
 	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds
index de8d09b..b1cae59 100644
--- a/board/freescale/m53017evb/u-boot.lds
+++ b/board/freescale/m53017evb/u-boot.lds
@@ -13,8 +13,6 @@ SECTIONS
   .text      :
   {
     arch/m68k/cpu/mcf532x/start.o	(.text*)
-    arch/m68k/cpu/mcf532x/built-in.o	(.text*)
-    arch/m68k/lib/built-in.o		(.text*)
 
     . = DEFINED(env_offset) ? env_offset : .;
     common/env_embedded.o	(.text*)
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 25480e4..2d07001 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -20,7 +20,7 @@
 void gpio_early_init_uart(void)
 {
 	/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
-	gpio_request(GPIO_PI3, NULL);
+	gpio_request(GPIO_PI3, "uart_en");
 	gpio_direction_output(GPIO_PI3, 0);
 }
 #endif
diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c
index 5427de5..ca40cea 100644
--- a/board/prodrive/alpr/nand.c
+++ b/board/prodrive/alpr/nand.c
@@ -93,19 +93,6 @@ static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 	}
 }
 
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++)
-		if (buf[i] != readb(&(alpr_ndfc->data)))
-			return i;
-
-	return 0;
-}
-#endif
-
 static int alpr_nand_dev_ready(struct mtd_info *mtd)
 {
 	/*
@@ -130,9 +117,6 @@ int board_nand_init(struct nand_chip *nand)
 	nand->read_byte  = alpr_nand_read_byte;
 	nand->write_buf  = alpr_nand_write_buf;
 	nand->read_buf   = alpr_nand_read_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-	nand->verify_buf = alpr_nand_verify_buf;
-#endif
 	nand->dev_ready  = alpr_nand_dev_ready;
 
 	return 0;
diff --git a/board/raspberrypi/rpi/Kconfig b/board/raspberrypi/rpi/Kconfig
deleted file mode 100644
index 6a538cf..0000000
--- a/board/raspberrypi/rpi/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_RPI
-
-config SYS_BOARD
-	default "rpi"
-
-config SYS_VENDOR
-	default "raspberrypi"
-
-config SYS_SOC
-	default "bcm2835"
-
-config SYS_CONFIG_NAME
-	default "rpi"
-
-endif
diff --git a/board/raspberrypi/rpi_2/Kconfig b/board/raspberrypi/rpi_2/Kconfig
deleted file mode 100644
index 032184d..0000000
--- a/board/raspberrypi/rpi_2/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_RPI_2
-
-config SYS_BOARD
-	default "rpi_2"
-
-config SYS_VENDOR
-	default "raspberrypi"
-
-config SYS_SOC
-	default "bcm2835"
-
-config SYS_CONFIG_NAME
-	default "rpi_2"
-
-endif
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c
index 1aca9fa..82f607b 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -58,16 +58,6 @@ void exynos_lcd_power_on(void)
 
 	mdelay(5);
 
-	/* TODO(ajaykumar.rs@samsung.com): Use device tree */
-	gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
-	gpio_direction_output(EXYNOS5420_GPIO_X35, 1);	/* EDP_SLP# */
-	mdelay(10);
-	gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
-	gpio_direction_output(EXYNOS5420_GPIO_Y77, 1);	/* EDP_RST# */
-	gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
-	gpio_direction_input(EXYNOS5420_GPIO_X26);	/* EDP_HPD */
-	gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
-
 	if (has_edp_bridge())
 		if (parade_init(gd->fdt_blob))
 			printf("%s: ps8625_init() failed\n", __func__);
@@ -75,11 +65,6 @@ void exynos_lcd_power_on(void)
 
 void exynos_backlight_on(unsigned int onoff)
 {
-	/* For PWM */
-	gpio_request(EXYNOS5420_GPIO_B20, "backlight_on");
-	gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1));
-	gpio_set_value(EXYNOS5420_GPIO_B20, 1);
-
 #ifdef CONFIG_POWER_TPS65090
 	tps65090_fet_enable(1);
 #endif
diff --git a/board/seco/Kconfig b/board/seco/Kconfig
new file mode 100644
index 0000000..dcb1ac8
--- /dev/null
+++ b/board/seco/Kconfig
@@ -0,0 +1,63 @@
+if TARGET_SECOMX6
+
+choice
+	prompt "SECO i.MX6 Board variant"
+
+config SECOMX6_Q7
+	bool "Q7"
+
+config SECOMX6_UQ7
+	bool "uQ7"
+
+config SECOMX6_USBC
+	bool "uSBC"
+
+endchoice
+
+choice
+	prompt "SECO i.MX6 SoC variant"
+
+config SECOMX6Q
+	bool "i.MX6Q"
+	select MX6Q
+
+config SECOMX6DL
+	bool "i.MX6DL"
+	select MX6DL
+
+config SECOMX6S
+	bool "i.MX6S"
+	select MX6S
+
+endchoice
+
+choice
+	prompt "DDR size"
+
+config SECOMX6_512MB
+	bool "512MB"
+
+config SECOMX6_1GB
+	bool "1GB"
+
+config SECOMX6_2GB
+	bool "2GB"
+
+config SECOMX6_4GB
+	bool "4GB"
+
+endchoice
+
+config IMX_CONFIG
+	default "board/seco/mx6quq7/mx6quq7-2g.cfg" if SECOMX6_UQ7 && SECOMX6Q && SECOMX6_2GB
+
+config SYS_BOARD
+	default "mx6quq7" if SECOMX6_UQ7 && SECOMX6Q
+
+config SYS_VENDOR
+	default "seco"
+
+config SYS_CONFIG_NAME
+	default "secomx6quq7" if SECOMX6_UQ7 && SECOMX6Q
+
+endif
diff --git a/board/seco/common/Makefile b/board/seco/common/Makefile
new file mode 100644
index 0000000..9e37ebb
--- /dev/null
+++ b/board/seco/common/Makefile
@@ -0,0 +1,2 @@
+
+obj-$(CONFIG_TARGET_SECOMX6) += mx6.o
diff --git a/board/seco/common/mx6.c b/board/seco/common/mx6.c
new file mode 100644
index 0000000..2f14f59
--- /dev/null
+++ b/board/seco/common/mx6.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015 ECA Sinters
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <micrel.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <i2c.h>
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+void seco_mx6_setup_uart_iomux(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP |	\
+			 PAD_CTL_SPEED_MED |	\
+			 PAD_CTL_DSE_40ohm |	\
+			 PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+void seco_mx6_setup_enet_iomux(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+int seco_mx6_rgmii_rework(struct phy_device *phydev)
+{
+	/* control data pad skew - devaddr = 0x02, register = 0x04 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+
+	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+	return 0;
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |	\
+			PAD_CTL_SPEED_LOW |	\
+			PAD_CTL_DSE_80ohm |	\
+			PAD_CTL_SRE_FAST  |	\
+			PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__SD4_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+void seco_mx6_setup_usdhc_iomux(int id)
+{
+	switch (id) {
+	case 3:
+		imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
+						 ARRAY_SIZE(usdhc3_pads));
+		break;
+
+	case 4:
+		imx_iomux_v3_setup_multiple_pads(usdhc4_pads,
+						 ARRAY_SIZE(usdhc4_pads));
+		break;
+
+	default:
+		printf("Warning: invalid usdhc id (%d)\n", id);
+		break;
+	}
+}
diff --git a/board/seco/common/mx6.h b/board/seco/common/mx6.h
new file mode 100644
index 0000000..a05db67
--- /dev/null
+++ b/board/seco/common/mx6.h
@@ -0,0 +1,9 @@
+#ifndef __SECO_COMMON_MX6_H
+#define __SECO_COMMON_MX6_H
+
+void seco_mx6_setup_uart_iomux(void);
+void seco_mx6_setup_enet_iomux(void);
+int seco_mx6_rgmii_rework(struct phy_device *phydev);
+void seco_mx6_setup_usdhc_iomux(int id);
+
+#endif /* __SECO_COMMON_MX6_H */
diff --git a/board/seco/mx6quq7/MAINTAINERS b/board/seco/mx6quq7/MAINTAINERS
new file mode 100644
index 0000000..60fd4ca
--- /dev/null
+++ b/board/seco/mx6quq7/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6QUQ7 BOARD
+M:	Boris Brezillon <boris.brezillon@free-electrons.com>
+S:	Maintained
+F:	board/seco/mx6quq7/
+F:	include/configs/secomx6quq7.h
+F:	configs/secomx6quq7_defconfig
diff --git a/board/seco/mx6quq7/Makefile b/board/seco/mx6quq7/Makefile
new file mode 100644
index 0000000..bbf1d68
--- /dev/null
+++ b/board/seco/mx6quq7/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 ECA Sinters
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6quq7.o
diff --git a/board/seco/mx6quq7/mx6quq7-2g.cfg b/board/seco/mx6quq7/mx6quq7-2g.cfg
new file mode 100644
index 0000000..159120e
--- /dev/null
+++ b/board/seco/mx6quq7/mx6quq7-2g.cfg
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2013 Seco USA Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION	2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM	sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* DDR IO TYPE */
+DATA 4, MX6_IOM_GRP_DDRPKE,	0x00000000
+DATA 4, MX6_IOM_GRP_DDR_TYPE,	0x000C0000
+
+/* DATA STROBE */
+DATA 4, MX6_IOM_DDRMODE_CTL,	0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0,	0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS1,	0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS2,	0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS3,	0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS4,	0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS5,	0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS6,	0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS7,	0x00000028
+
+/* DATA */
+DATA 4, MX6_IOM_GRP_DDRMODE,    0x00020000
+DATA 4, MX6_IOM_GRP_B0DS,	0x00000028
+DATA 4, MX6_IOM_GRP_B1DS,	0x00000028
+DATA 4, MX6_IOM_GRP_B2DS,	0x00000028
+DATA 4, MX6_IOM_GRP_B3DS,	0x00000028
+DATA 4, MX6_IOM_GRP_B4DS,	0x00000028
+DATA 4, MX6_IOM_GRP_B5DS,	0x00000028
+DATA 4, MX6_IOM_GRP_B6DS,	0x00000028
+DATA 4, MX6_IOM_GRP_B7DS,	0x00000028
+DATA 4, MX6_IOM_DRAM_DQM0,      0x00000028
+DATA 4, MX6_IOM_DRAM_DQM1,      0x00000028
+DATA 4, MX6_IOM_DRAM_DQM2,      0x00000028
+DATA 4, MX6_IOM_DRAM_DQM3,      0x00000028
+DATA 4, MX6_IOM_DRAM_DQM4,      0x00000028
+DATA 4, MX6_IOM_DRAM_DQM5,      0x00000028
+DATA 4, MX6_IOM_DRAM_DQM6,      0x00000028
+DATA 4, MX6_IOM_DRAM_DQM7,      0x00000028
+/* ADDRESS */
+DATA 4, MX6_IOM_GRP_ADDDS,	0x00000028
+DATA 4, MX6_IOM_DRAM_CAS,       0x00000028
+DATA 4, MX6_IOM_DRAM_RAS,       0x00000028
+
+/* CONTROL */
+DATA 4, MX6_IOM_GRP_CTLDS,	0x00000030
+DATA 4, MX6_IOM_DRAM_RESET,     0x00000028
+DATA 4, MX6_IOM_DRAM_SDBA2,     0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0,    0x00000028
+DATA 4, MX6_IOM_DRAM_SDODT1,    0x00000028
+
+/* CLOCK */
+DATA 4, MX6_IOM_DRAM_SDCLK_0,	0x00000028
+DATA 4, MX6_IOM_DRAM_SDCLK_1,	0x00000028
+
+/*
+ * DDR3 SETTINGS
+ * Read Data Bit Delay
+ */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL,	0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL,	0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL,	0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL,	0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL,	0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL,	0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL,	0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL,	0x33333333
+
+
+/* Write Leveling */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0,        0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1,        0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0,        0x001F0001
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1,        0x001F001F
+
+/* DQS gating, read delay, write delay calibration values */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0,  0x431A0326
+DATA 4, MX6_MMDC_P0_MPDGCTRL1,  0x0323031B
+DATA 4, MX6_MMDC_P1_MPDGCTRL0,  0x433F0340
+DATA 4, MX6_MMDC_P1_MPDGCTRL1,  0x0345031C
+
+/* Read calibration */
+DATA 4, MX6_MMDC_P0_MPRDDLCTL,  0x40343137
+DATA 4, MX6_MMDC_P1_MPRDDLCTL,  0x40372F45
+
+/* write calibration */
+DATA 4, MX6_MMDC_P0_MPWRDLCTL,  0x32414741
+DATA 4, MX6_MMDC_P1_MPWRDLCTL,  0x4731473C
+
+/* Complete calibration by forced measurement: */
+DATA 4, MX6_MMDC_P0_MPMUR0,     0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0,     0x00000800
+
+/*
+ * MMDC init:
+ * in DDR3, 64-bit mode, only MMDC0 is init
+ */
+DATA 4, MX6_MMDC_P0_MDPDC,	0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC,	0x09444040
+
+DATA 4, MX6_MMDC_P0_MDCFG0,	0x898E7955
+DATA 4, MX6_MMDC_P0_MDCFG1,	0xFF328F64
+DATA 4, MX6_MMDC_P0_MDCFG2,	0x01FF00DB
+
+DATA 4, MX6_MMDC_P0_MDMISC,	0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD,	0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR,       0x008E1023
+
+/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */
+DATA 4, MX6_MMDC_P0_MDASP,	0x00000047
+
+/* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */
+DATA 4, MX6_MMDC_P0_MDCTL,	0x841A0000
+
+/* Initialize DDR3 on CS_0 and CS_1 */
+DATA 4, MX6_MMDC_P0_MDSCR,	0x02088032
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00048031
+
+/* P0 01c */
+/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */
+DATA 4, MX6_MMDC_P0_MDSCR,	0x09408030
+
+/*ZQ - Calibrationi */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+DATA 4, MX6_MMDC_P0_MDSCR,      0x04008040
+DATA 4, MX6_MMDC_P0_MDREF,      0x00007800
+
+DATA 4, MX6_MMDC_P0_MPODTCTRL,  0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL,  0x00022227
+
+DATA 4, MX6_MMDC_P0_MDPDC,      0x00025576
+
+DATA 4, MX6_MMDC_P0_MAPSR,      0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR,      0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
+
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
diff --git a/board/seco/mx6quq7/mx6quq7.c b/board/seco/mx6quq7/mx6quq7.c
new file mode 100644
index 0000000..ea1d4b8
--- /dev/null
+++ b/board/seco/mx6quq7/mx6quq7.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015 ECA Sinters
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <micrel.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <i2c.h>
+
+#include "../common/mx6.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	seco_mx6_setup_uart_iomux();
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	seco_mx6_rgmii_rework(phydev);
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	uint32_t base = IMX_FEC_BASE;
+	struct mii_dev *bus = NULL;
+	struct phy_device *phydev = NULL;
+	int ret = 0;
+
+	seco_mx6_setup_enet_iomux();
+
+#ifdef CONFIG_FEC_MXC
+	bus = fec_get_miibus(base, -1);
+	if (!bus)
+		return -ENOMEM;
+
+	/* scan phy 4,5,6,7 */
+	phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+	if (!phydev) {
+		free(bus);
+		return -ENOMEM;
+	}
+
+	printf("using phy at %d\n", phydev->addr);
+	ret  = fec_probe(bis, -1, base, bus, phydev);
+	if (ret) {
+		free(phydev);
+		free(bus);
+		printf("FEC MXC: %s:failed\n", __func__);
+	}
+#endif
+
+	return ret;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC2_BASE_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	u32 index = 0;
+	int ret;
+
+	/*
+	 * Following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    eMMC on Board
+	 * mmc1                    Ext SD
+	 */
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			seco_mx6_setup_usdhc_iomux(3);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			usdhc_cfg[0].max_bus_width = 4;
+			break;
+		case 1:
+			seco_mx6_setup_usdhc_iomux(4);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+			usdhc_cfg[1].max_bus_width = 4;
+			break;
+
+		default:
+			printf("Warning: %d exceed maximum number of SD ports %d\n",
+			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D4__GPIO2_IO04 |
+			       MUX_PAD_CTRL(NO_PAD_CTRL));
+
+	gpio_direction_output(IMX_GPIO_NR(2, 4), 0);
+
+	/* Set Low */
+	gpio_set_value(IMX_GPIO_NR(2, 4), 0);
+	udelay(1000);
+
+	/* Set High */
+	gpio_set_value(IMX_GPIO_NR(2, 4), 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: SECO uQ7\n");
+
+	return 0;
+}
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index 7394478..15e6ea6 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -18,9 +18,6 @@ static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
 static u_char sc_nand_read_byte(struct mtd_info *mtd);
 static u16 sc_nand_read_word(struct mtd_info *mtd);
 static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
-#endif
 static int sc_nand_device_ready(struct mtd_info *mtdinfo);
 
 #define FPGA_NAND_CMD_MASK		(0x7 << 28)
@@ -102,25 +99,6 @@ static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 	}
 }
 
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-/**
- * sc_nand_verify_buf -  Verify chip data against buffer
- * @mtd:	MTD device structure
- * @buf:	buffer containing the data to compare
- * @len:	number of bytes to compare
- */
-static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++) {
-		if (buf[i] != sc_nand_read_byte(mtd));
-			return -EFAULT;
-	}
-	return 0;
-}
-#endif
-
 /**
  * sc_nand_device_ready - Check the NAND device is ready for next command.
  * @mtd:	MTD device structure
@@ -178,9 +156,6 @@ int board_nand_init(struct nand_chip *nand)
 	nand->read_word = sc_nand_read_word;
 	nand->write_buf = sc_nand_write_buf;
 	nand->read_buf = sc_nand_read_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-	nand->verify_buf = sc_nand_verify_buf;
-#endif
 
 	return 0;
 }
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 9d0eb91..2fcab60 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -132,6 +132,10 @@ endchoice
 
 endif
 
+config SYS_CLK_FREQ
+	default 912000000 if MACH_SUN7I
+	default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
+
 config SYS_CONFIG_NAME
 	default "sun4i" if MACH_SUN4I
 	default "sun5i" if MACH_SUN5I
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index ef3c937..be48213 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -21,6 +21,7 @@ F:	configs/A13-OLinuXinoM_defconfig
 F:	configs/Auxtek-T004_defconfig
 F:	configs/mk802_a10s_defconfig
 F:	configs/r7-tv-dongle_defconfig
+F:	configs/UTOO_P66_defconfig
 F:	include/configs/sun6i.h
 F:	configs/CSQ_CS908_defconfig
 F:	configs/Mele_M9_defconfig
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index e1891d1..808bf82 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -215,7 +215,7 @@ void sunxi_board_init(void)
 	 * assured it's being powered with suitable core voltage
 	 */
 	if (!power_failed)
-		clock_set_pll1(CONFIG_CLK_FULL_SPEED);
+		clock_set_pll1(CONFIG_SYS_CLK_FREQ);
 	else
 		printf("Failed to set core voltage! Can't set CPU frequency\n");
 }
diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
index d1271ff..7742049 100644
--- a/board/synopsys/axs101/axs101.c
+++ b/board/synopsys/axs101/axs101.c
@@ -27,9 +27,9 @@ int board_mmc_init(bd_t *bis)
 	host->ioaddr = (void *)ARC_DWMMC_BASE;
 	host->buswidth = 4;
 	host->dev_index = 0;
-	host->bus_hz = 25000000;
+	host->bus_hz = 50000000;
 
-	add_dwmci(host, 52000000, 400000);
+	add_dwmci(host, host->bus_hz, 400000);
 
 	return 0;
 }
diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig
index 722f9d5..7cb006f 100644
--- a/board/ti/am335x/Kconfig
+++ b/board/ti/am335x/Kconfig
@@ -47,10 +47,4 @@ config DM_GPIO
 config DM_SERIAL
 	default y if DM
 
-config SYS_MALLOC_F
-	default y if DM
-
-config SYS_MALLOC_F_LEN
-	default 0x400 if DM
-
 endif
diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.h b/board/toradex/colibri_t20-common/colibri_t20-common.h
deleted file mode 100644
index 1fe53f6..0000000
--- a/board/toradex/colibri_t20-common/colibri_t20-common.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- *  Copyright (C) 2012 Lucas Stach
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-void colibri_t20_common_pin_mux_usb(void);
diff --git a/board/toradex/colibri_t20_iris/Kconfig b/board/toradex/colibri_t20/Kconfig
index 4bf7278..7f373b2 100644
--- a/board/toradex/colibri_t20_iris/Kconfig
+++ b/board/toradex/colibri_t20/Kconfig
@@ -1,12 +1,12 @@
-if TARGET_COLIBRI_T20_IRIS
+if TARGET_COLIBRI_T20
 
 config SYS_BOARD
-	default "colibri_t20_iris"
+	default "colibri_t20"
 
 config SYS_VENDOR
 	default "toradex"
 
 config SYS_CONFIG_NAME
-	default "colibri_t20_iris"
+	default "colibri_t20"
 
 endif
diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS
new file mode 100644
index 0000000..b251c00
--- /dev/null
+++ b/board/toradex/colibri_t20/MAINTAINERS
@@ -0,0 +1,7 @@
+COLIBRI_T20
+M:	Lucas Stach <dev@lynxeye.de>
+S:	Maintained
+F:	board/toradex/colibri_t20/
+F:	include/configs/colibri_t20.h
+F:	configs/colibri_t20_defconfig
+F:	arch/arm/dts/tegra20-colibri.dtb
diff --git a/board/toradex/colibri_t20/Makefile b/board/toradex/colibri_t20/Makefile
new file mode 100644
index 0000000..86f78d9
--- /dev/null
+++ b/board/toradex/colibri_t20/Makefile
@@ -0,0 +1,9 @@
+#
+#  (C) Copyright 2012 Lucas Stach
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include $(srctree)/board/nvidia/common/common.mk
+
+obj-y	+= colibri_t20.o
diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.c b/board/toradex/colibri_t20/colibri_t20.c
index 58a9916..8ae9ccf 100644
--- a/board/toradex/colibri_t20-common/colibri_t20-common.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -9,27 +9,57 @@
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch-tegra/board.h>
+#include <asm/gpio.h>
 
-#include "colibri_t20-common.h"
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+	pinmux_tristate_disable(PMUX_PINGRP_GMB);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_NAND
+void pin_mux_nand(void)
+{
+	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
+
+	/*
+	 * configure pingroup ATC to something unrelated to
+	 * avoid ATC overriding KBC
+	 */
+	pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI);
+}
+#endif
 
 #ifdef CONFIG_USB_EHCI_TEGRA
-void colibri_t20_common_pin_mux_usb(void)
+void pin_mux_usb(void)
 {
 	/* module internal USB bus to connect ethernet chipset */
 	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+
 	/* ULPI reference clock output */
 	pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
 	pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+
 	/* PHY reset GPIO */
 	pinmux_tristate_disable(PMUX_PINGRP_UAC);
+
 	/* VBus GPIO */
 	pinmux_tristate_disable(PMUX_PINGRP_DTE);
-}
-#endif
 
-#ifdef CONFIG_TEGRA_NAND
-void pin_mux_nand(void)
-{
-	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
+	/* Reset ASIX using LAN_RESET */
+	gpio_request(GPIO_PV4, "LAN_RESET");
+	gpio_direction_output(GPIO_PV4, 0);
+	pinmux_tristate_disable(PMUX_PINGRP_GPV);
+	udelay(5);
+	gpio_set_value(GPIO_PV4, 1);
+
+	/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
+	pinmux_tristate_disable(PMUX_PINGRP_SPIG);
 }
 #endif
diff --git a/board/toradex/colibri_t20_iris/MAINTAINERS b/board/toradex/colibri_t20_iris/MAINTAINERS
deleted file mode 100644
index c68955b..0000000
--- a/board/toradex/colibri_t20_iris/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-COLIBRI_T20_IRIS BOARD
-M:	Lucas Stach <dev@lynxeye.de>
-S:	Maintained
-F:	board/toradex/colibri_t20_iris/
-F:	include/configs/colibri_t20_iris.h
-F:	configs/colibri_t20_iris_defconfig
diff --git a/board/toradex/colibri_t20_iris/Makefile b/board/toradex/colibri_t20_iris/Makefile
deleted file mode 100644
index ebeac70..0000000
--- a/board/toradex/colibri_t20_iris/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-#  (C) Copyright 2012 Lucas Stach
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ../../nvidia/common/board.o
-obj-y	+= ../colibri_t20-common/colibri_t20-common.o
-obj-y	+= colibri_t20_iris.o
diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c
deleted file mode 100644
index 49c74f3..0000000
--- a/board/toradex/colibri_t20_iris/colibri_t20_iris.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  Copyright (C) 2012 Lucas Stach
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/board.h>
-
-#include "../colibri_t20-common/colibri_t20-common.h"
-
-#ifdef CONFIG_USB_EHCI_TEGRA
-void pin_mux_usb(void)
-{
-	colibri_t20_common_pin_mux_usb();
-
-	/* USB 1 aka Tegra USB port 3 VBus*/
-	pinmux_tristate_disable(PMUX_PINGRP_SPIG);
-}
-#endif
-
-#ifdef CONFIG_TEGRA_MMC
-/*
- * Routine: pin_mux_mmc
- * Description: setup the pin muxes/tristate values for the SDMMC(s)
- */
-void pin_mux_mmc(void)
-{
-	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
-	pinmux_tristate_disable(PMUX_PINGRP_GMB);
-}
-#endif
diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS
index 382e921..e0dc4fe 100644
--- a/board/xilinx/zynq/MAINTAINERS
+++ b/board/xilinx/zynq/MAINTAINERS
@@ -1,6 +1,5 @@
 ZYNQ BOARD
 M:	Michal Simek <monstr@monstr.eu>
-M:	Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 S:	Maintained
 F:	board/xilinx/zynq/
 F:	include/configs/zynq*.h