Merge branch 'master' into hpc2

19 files changed, 2659 insertions, 10 deletions

diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index ccf6f0c..ff211ae 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -31,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
+ulong flash_get_size (ulong base, int banknum);
+
 int board_early_init_f(void)
 {
 	unsigned long sdr0_cust0;
@@ -152,6 +154,11 @@ int misc_init_r(void)
 	 */
 
 	/* Re-do sizing to get full correct info */
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 	mtdcr(ebccfga, pb3cr);
 #else
@@ -192,9 +199,10 @@ int misc_init_r(void)
 #endif
 	mtdcr(ebccfgd, pbcr);
 
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size(gd->bd->bi_flashstart, 0);
 
 #ifdef CFG_ENV_IS_IN_FLASH
 	/* Monitor protection ON by default */
diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c
index 40a827c..f5c3dd9 100644
--- a/board/dave/PPChameleonEVB/nand.c
+++ b/board/dave/PPChameleonEVB/nand.c
@@ -105,7 +105,7 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
  * Members with a "?" were not set in the merged testing-NAND branch,
  * so they are not set here either.
  */
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 
 	nand->hwcontrol = ppchameleonevb_hwcontrol;
@@ -113,5 +113,6 @@ void board_nand_init(struct nand_chip *nand)
 	nand->eccmode = NAND_ECC_SOFT;
 	nand->chip_delay = NAND_BIG_DELAY_US;
 	nand->options = NAND_SAMSUNG_LP_OPTIONS;
+	return 0;
 }
 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
diff --git a/board/delta/nand.c b/board/delta/nand.c
index fe648fc..d170938 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -448,7 +448,7 @@ static void dfc_gpio_init(void)
  * Members with a "?" were not set in the merged testing-NAND branch,
  * so they are not set here either.
  */
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 	unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
 
@@ -576,6 +576,7 @@ void board_nand_init(struct nand_chip *nand)
 	nand->cmdfunc = dfc_cmdfunc;
 	nand->autooob = &delta_oob;
 	nand->badblock_pattern = &delta_bbt_descr;
+	return 0;
 }
 
 #else
diff --git a/board/idmr/Makefile b/board/idmr/Makefile
new file mode 100644
index 0000000..cf07cf4
--- /dev/null
+++ b/board/idmr/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/idmr/config.mk b/board/idmr/config.mk
new file mode 100644
index 0000000..f7c2258
--- /dev/null
+++ b/board/idmr/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xff800000
diff --git a/board/idmr/flash.c b/board/idmr/flash.c
new file mode 100644
index 0000000..ba9b009
--- /dev/null
+++ b/board/idmr/flash.c
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define FLASH_BANK_SIZE 0x800000
+#define EN29LV640 0x227e227e
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (EN29LV640 & FLASH_TYPEMASK):
+		printf ("EN29LV640 (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+      Done:
+	return;
+}
+
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(EN29LV640 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured to many flash banks!\n");
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + 0x10000 * j;
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + 0x30000, &flash_info[0]);
+
+	return size;
+}
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	iflag = disable_interrupts ();
+
+	printf ("\n");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		set_timer (0);
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr =
+				(volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	printf("Waiting 10 ms...");
+	 udelay (10000);
+
+/*	for (i = 0; i < 10 * 1000 * 1000; ++i)
+		asm(" nop");
+*/
+
+	printf("done\n");
+	if (iflag)
+		enable_interrupts ();
+
+
+	return rc;
+}
+
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int iflag;
+	int chip1;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	set_timer (0);
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	}
+
+#if 0
+	if (cnt & 1) {
+		printf ("odd transfer sizes not supported\n");
+		return ERR_ALIGN;
+	}
+#endif
+
+	wp = addr;
+
+	if (addr & 1) {
+		data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
+							  src);
+		if ((rc = write_word (info, wp - 1, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src) << 8) |
+			*((volatile u8 *) (wp + 1));
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}
diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c
new file mode 100644
index 0000000..58cdba1
--- /dev/null
+++ b/board/idmr/idmr.c
@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5271.h>
+#include <asm/immap_5271.h>
+
+int checkboard (void) {
+	puts ("Board: iDMR\n");
+	return 0;
+};
+
+long int initdram (int board_type) {
+	int i;
+
+	/*
+	 * After reset, CS0 is configured to cover entire address space. We
+	 * need to configure it to its proper values, so that writes to
+	 * CFG_SDRAM_BASE and vicinity during SDRAM controller setup below do
+	 * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
+	 */
+
+	/* Flash chipselect, CS0 */
+	/* ;CSAR0: Flash at 0xFF800000 */
+	mbar_writeShort(0x0080, 0xFF80);
+
+	/* CSCR0: Flash 6 waits, 16bit */
+	mbar_writeShort(0x008A, 0x1980);
+
+	/* CSMR0: Flash 8MB, R/W, valid */
+	mbar_writeLong(0x0084, 0x007F0001);
+
+
+	/*
+	 * SDRAM configuration proper
+	 */
+
+	/*
+	 * Address/Data Pin Assignment Reg.: enable address lines 23-21; do
+	 * not enable data pins D[15:0], as we have 16 bit port to SDRAM
+	 */
+	mbar_writeByte(MCF_GPIO_PAR_AD,
+			MCF_GPIO_AD_ADDR23 |
+			MCF_GPIO_AD_ADDR22 |
+			MCF_GPIO_AD_ADDR21);
+
+	/* No need to configure BS pins - reset values are OK */
+
+	/* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */
+	mbar_writeByte(MCF_GPIO_PAR_CS, 0x00);
+
+	/* SDRAM Control Pin Assignment Reg. */
+	mbar_writeByte(MCF_GPIO_PAR_SDRAM,
+			MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */
+			MCF_GPIO_SDRAM_SDWE |
+			MCF_GPIO_SDRAM_SCAS |
+			MCF_GPIO_SDRAM_SRAS |
+			MCF_GPIO_SDRAM_SCKE |
+			MCF_GPIO_SDRAM_SDCS_01);
+
+	/*
+	 * Wait 100us.  We run the bus at 50Mhz, one cycle is 20ns. So 5
+	 * iterations will do, but we do 10 just to be safe.
+	 */
+	for (i = 0; i < 10; ++i)
+		asm(" nop");
+
+
+	/* 1. Initialize DRAM Control Register: DCR */
+	mbar_writeShort(MCF_SDRAMC_DCR,
+			MCF_SDRAMC_DCR_RTIM(0x10) |	/* 65ns */
+			MCF_SDRAMC_DCR_RC(0x60));	/* 1562 cycles */
+
+
+	/*
+	 * 2. Initialize DACR0
+	 *
+	 * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1)
+	 * CBM: cmd at A20, bank select bits 21 and up
+	 * PS: 16 bit
+	 */
+	mbar_writeLong(MCF_SDRAMC_DACR0,
+			MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) |
+			MCF_SDRAMC_DACRn_BA(0x00) |
+			MCF_SDRAMC_DACRn_CASL(0x03) |
+			MCF_SDRAMC_DACRn_CBM(0x03) |
+			MCF_SDRAMC_DACRn_PS(0x03));
+
+	/* Initialize DMR0 */
+	mbar_writeLong(MCF_SDRAMC_DMR0,
+			MCF_SDRAMC_DMRn_BAM_16M |
+			MCF_SDRAMC_DMRn_V);
+
+
+	/* 3. Set IP bit in DACR to initiate PALL command */
+	mbar_writeLong(MCF_SDRAMC_DACR0,
+			mbar_readLong(MCF_SDRAMC_DACR0) |
+			MCF_SDRAMC_DACRn_IP);
+
+	/* Write to this block to initiate precharge */
+	*(volatile u16 *)(CFG_SDRAM_BASE) = 0xa5a5;
+
+	/*
+	 * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
+	 * wait a wee longer, just to be safe.
+	 */
+	for (i = 0; i < 5; ++i)
+		asm(" nop");
+
+
+	/* 4. Set RE bit in DACR */
+	mbar_writeLong(MCF_SDRAMC_DACR0,
+			mbar_readLong(MCF_SDRAMC_DACR0) |
+			MCF_SDRAMC_DACRn_RE);
+
+	/*
+	 * Wait for at least 8 auto refresh cycles to occur, i.e. at least
+	 * 781 bus cycles.
+	 */
+	for (i = 0; i < 1000; ++i)
+		asm(" nop");
+
+	/* Finish the configuration by issuing the MRS */
+	mbar_writeLong(MCF_SDRAMC_DACR0,
+			mbar_readLong(MCF_SDRAMC_DACR0) |
+			MCF_SDRAMC_DACRn_MRS);
+
+	/*
+	 * Write to the SDRAM Mode Register A0-A11 = 0x400
+	 *
+	 * Write Burst Mode = Programmed Burst Length
+	 * Op Mode = Standard Op
+	 * CAS Latency = 3
+	 * Burst Type = Sequential
+	 * Burst Length = 1
+	 */
+	*(volatile u32 *)(CFG_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
+
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+};
+
+
+int testdram (void) {
+
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds
new file mode 100644
index 0000000..69f3179
--- /dev/null
+++ b/board/idmr/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+GROUP(libgcc.a)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf52x2/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile
index 75808cb..5869119 100644
--- a/board/mcc200/Makefile
+++ b/board/mcc200/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o lcd.o
+COBJS	:= $(BOARD).o lcd.o auto_update.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c
new file mode 100644
index 0000000..63e4139
--- /dev/null
+++ b/board/mcc200/auto_update.c
@@ -0,0 +1,457 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+
+#ifdef CFG_HUSH_PARSER
+#include <hush.h>
+#endif
+
+
+#ifdef CONFIG_AUTO_UPDATE
+
+#ifndef CONFIG_USB_OHCI
+#error "must define CONFIG_USB_OHCI"
+#endif
+
+#ifndef CONFIG_USB_STORAGE
+#error "must define CONFIG_USB_STORAGE"
+#endif
+
+#ifndef CFG_HUSH_PARSER
+#error "must define CFG_HUSH_PARSER"
+#endif
+
+#if !(CONFIG_COMMANDS & CFG_CMD_FAT)
+#error "must define CFG_CMD_FAT"
+#endif
+
+/*
+ * Check whether a USB memory stick is plugged in.
+ * If one is found:
+ *	1) if prepare.img ist found load it into memory. If it is
+ *		valid then run it.
+ *	2) if preinst.img is found load it into memory. If it is
+ *		valid then run it. Update the EEPROM.
+ *	3) if firmw_01.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	4) if kernl_01.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	5) if app.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	6) if disk.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	7) if postinst.img is found load it into memory. If it is
+ *		valid then run it. Update the EEPROM.
+ */
+
+#undef AU_DEBUG
+
+#undef debug
+#ifdef	AU_DEBUG
+#define debug(fmt,args...)	printf (fmt ,##args)
+#else
+#define debug(fmt,args...)
+#endif	/* AU_DEBUG */
+
+/* possible names of files on the USB stick. */
+#define AU_FIRMWARE	"u-boot.img"
+#define AU_KERNEL	"kernel.img"
+
+struct flash_layout {
+	long start;
+	long end;
+};
+
+/* layout of the FLASH. ST = start address, ND = end address. */
+#define AU_FL_FIRMWARE_ST	0xfC000000
+#define AU_FL_FIRMWARE_ND	0xfC03FFFF
+#define AU_FL_KERNEL_ST		0xfC0C0000
+#define AU_FL_KERNEL_ND		0xfC1BFFFF
+
+static int au_usb_stor_curr_dev; /* current device */
+
+/* index of each file in the following arrays */
+#define IDX_FIRMWARE	0
+#define IDX_KERNEL	1
+
+/* max. number of files which could interest us */
+#define AU_MAXFILES 2
+
+/* pointers to file names */
+char *aufile[AU_MAXFILES];
+
+/* sizes of flash areas for each file */
+long ausize[AU_MAXFILES];
+
+/* array of flash areas start and end addresses */
+struct flash_layout aufl_layout[AU_MAXFILES] = { \
+	{AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND,}, \
+	{AU_FL_KERNEL_ST, AU_FL_KERNEL_ND,}, \
+};
+
+/* where to load files into memory */
+#define LOAD_ADDR ((unsigned char *)0x00200000)
+
+/* the app is the largest image */
+#define MAX_LOADSZ ausize[IDX_KERNEL]
+
+/*i2c address of the keypad status*/
+#define I2C_PSOC_KEYPAD_ADDR	0x53
+
+/* keypad mask */
+#define KEYPAD_ROW	3
+#define KEYPAD_COL	3
+#define KEYPAD_MASK_LO	((1<<(KEYPAD_COL-1+(KEYPAD_ROW*4-4)))&0xFF)
+#define KEYPAD_MASK_HI	((1<<(KEYPAD_COL-1+(KEYPAD_ROW*4-4)))>>8)
+
+/* externals */
+extern int fat_register_device(block_dev_desc_t *, int);
+extern int file_fat_detectfs(void);
+extern long file_fat_read(const char *, void *, unsigned long);
+extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
+extern int flash_sect_erase(ulong, ulong);
+extern int flash_sect_protect (int, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
+/* change char* to void* to shutup the compiler */
+extern block_dev_desc_t *get_dev (char*, int);
+extern int u_boot_hush_start(void);
+
+int au_check_cksum_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) {
+		printf ("Image %s bad total SIZE\n", aufile[idx]);
+		return -1;
+	}
+	/* check the data CRC */
+	checksum = ntohl(hdr->ih_dcrc);
+
+	if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) != checksum) {
+		printf ("Image %s bad data checksum\n", aufile[idx]);
+		return -1;
+	}
+	return 0;
+}
+
+int au_check_header_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+	unsigned char buf[4];
+
+	hdr = (image_header_t *)LOAD_ADDR;
+	/* check the easy ones first */
+#undef CHECK_VALID_DEBUG
+#ifdef CHECK_VALID_DEBUG
+	printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC);
+	printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_ARM);
+	printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes);
+	printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL);
+#endif
+	if (nbytes < sizeof(*hdr)) {
+		printf ("Image %s bad header SIZE\n", aufile[idx]);
+		return -1;
+	}
+	if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_PPC) {
+		printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]);
+		return -1;
+	}
+	/* check the hdr CRC */
+	checksum = ntohl(hdr->ih_hcrc);
+	hdr->ih_hcrc = 0;
+
+	if (crc32 (0, (uchar *)hdr, sizeof(*hdr)) != checksum) {
+		printf ("Image %s bad header checksum\n", aufile[idx]);
+		return -1;
+	}
+	hdr->ih_hcrc = htonl(checksum);
+	/* check the type - could do this all in one gigantic if() */
+	if ((idx == IDX_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_KERNEL) && (hdr->ih_type != IH_TYPE_KERNEL)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	/* recycle checksum */
+	checksum = ntohl(hdr->ih_size);
+	/* for kernel and app the image header must also fit into flash */
+	if (idx != IDX_FIRMWARE)
+		checksum += sizeof(*hdr);
+	/* check the size does not exceed space in flash. HUSH scripts */
+	/* all have ausize[] set to 0 */
+	if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
+		printf ("Image %s is bigger than FLASH\n", aufile[idx]);
+		return -1;
+	}
+	return 0;
+}
+
+int au_do_update(int idx, long sz)
+{
+	image_header_t *hdr;
+	char *addr;
+	long start, end;
+	int off, rc;
+	uint nbytes;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	/* execute a script */
+	if (hdr->ih_type == IH_TYPE_SCRIPT) {
+		addr = (char *)((char *)hdr + sizeof(*hdr));
+		/* stick a NULL at the end of the script, otherwise */
+		/* parse_string_outer() runs off the end. */
+		addr[ntohl(hdr->ih_size)] = 0;
+		addr += 8;
+		parse_string_outer(addr, FLAG_PARSE_SEMICOLON);
+		return 0;
+	}
+
+	start = aufl_layout[idx].start;
+	end = aufl_layout[idx].end;
+
+	/* unprotect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE) {
+#undef AU_UPDATE_TEST
+#ifdef AU_UPDATE_TEST
+		/* erase it where Linux goes */
+		start = aufl_layout[1].start;
+		end = aufl_layout[1].end;
+#endif
+		flash_sect_protect(0, start, end);
+	}
+
+	/*
+	 * erase the address range.
+	 */
+	debug ("flash_sect_erase(%lx, %lx);\n", start, end);
+	flash_sect_erase(start, end);
+	wait_ms(100);
+	/* strip the header - except for the kernel and ramdisk */
+	if (hdr->ih_type == IH_TYPE_KERNEL) {
+		addr = (char *)hdr;
+		off = sizeof(*hdr);
+		nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
+	} else {
+		addr = (char *)((char *)hdr + sizeof(*hdr));
+#ifdef AU_UPDATE_TEST
+		/* copy it to where Linux goes */
+		if (idx == IDX_FIRMWARE)
+			start = aufl_layout[1].start;
+#endif
+		off = 0;
+		nbytes = ntohl(hdr->ih_size);
+	}
+
+	/* copy the data from RAM to FLASH */
+	debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
+	rc = flash_write(addr, start, nbytes);
+	if (rc != 0) {
+		printf("Flashing failed due to error %d\n", rc);
+		return -1;
+	}
+
+	/* check the dcrc of the copy */
+	if (crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) {
+		printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]);
+		return -1;
+	}
+
+	/* protect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE)
+		flash_sect_protect(1, start, end);
+	return 0;
+}
+
+/*
+ * this is called from board_init() after the hardware has been set up
+ * and is usable. That seems like a good time to do this.
+ * Right now the return value is ignored.
+ */
+int do_auto_update(void)
+{
+	block_dev_desc_t *stor_dev;
+	long sz;
+	int i, res, bitmap_first, cnt, old_ctrlc, got_ctrlc;
+	char *env;
+	long start, end;
+	char keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0};
+
+	/*
+	 * Read keypad status
+	 */
+	i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2);
+	wait_ms(500);
+	i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2);
+
+	/*
+	 * Check keypad
+	 */
+	if ( !(keypad_status1[0] & KEYPAD_MASK_HI) ||
+	      (keypad_status1[0] != keypad_status2[0])) {
+		return 0;
+	}
+	if ( !(keypad_status1[1] & KEYPAD_MASK_LO) ||
+	      (keypad_status1[1] != keypad_status2[1])) {
+		return 0;
+	}
+	au_usb_stor_curr_dev = -1;
+	/* start USB */
+	if (usb_stop() < 0) {
+		debug ("usb_stop failed\n");
+		return -1;
+	}
+	if (usb_init() < 0) {
+		debug ("usb_init failed\n");
+		return -1;
+	}
+	/*
+	 * check whether a storage device is attached (assume that it's
+	 * a USB memory stick, since nothing else should be attached).
+	 */
+	au_usb_stor_curr_dev = usb_stor_scan(0);
+	if (au_usb_stor_curr_dev == -1) {
+		debug ("No device found. Not initialized?\n");
+		return -1;
+	}
+	/* check whether it has a partition table */
+	stor_dev = get_dev("usb", 0);
+	if (stor_dev == NULL) {
+		debug ("uknown device type\n");
+		return -1;
+	}
+	if (fat_register_device(stor_dev, 1) != 0) {
+		debug ("Unable to use USB %d:%d for fatls\n",
+			au_usb_stor_curr_dev, 1);
+		return -1;
+	}
+	if (file_fat_detectfs() != 0) {
+		debug ("file_fat_detectfs failed\n");
+	}
+
+	/* initialize the array of file names */
+	memset(aufile, 0, sizeof(aufile));
+	aufile[IDX_FIRMWARE] = AU_FIRMWARE;
+	aufile[IDX_KERNEL] = AU_KERNEL;
+	/* initialize the array of flash sizes */
+	memset(ausize, 0, sizeof(ausize));
+	ausize[IDX_FIRMWARE] = (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST;
+	ausize[IDX_KERNEL] = (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST;
+	/*
+	 * now check whether start and end are defined using environment
+	 * variables.
+	 */
+	start = -1;
+	end = 0;
+	env = getenv("firmware_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("firmware_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_FIRMWARE] = (end + 1) - start;
+		aufl_layout[0].start = start;
+		aufl_layout[0].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("kernel_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("kernel_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_KERNEL] = (end + 1) - start;
+		aufl_layout[1].start = start;
+		aufl_layout[1].end = end;
+	}
+	/* make certain that HUSH is runnable */
+	u_boot_hush_start();
+	/* make sure that we see CTRL-C and save the old state */
+	old_ctrlc = disable_ctrlc(0);
+
+	bitmap_first = 0;
+	/* just loop thru all the possible files */
+	for (i = 0; i < AU_MAXFILES; i++) {
+		/* just read the header */
+		sz = file_fat_read(aufile[i], LOAD_ADDR, sizeof(image_header_t));
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, sizeof(image_header_t));
+		if (sz <= 0 || sz < sizeof(image_header_t)) {
+			debug ("%s not found\n", aufile[i]);
+			continue;
+		}
+		if (au_check_header_valid(i, sz) < 0) {
+			debug ("%s header not valid\n", aufile[i]);
+			continue;
+		}
+		sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ);
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, sizeof(image_header_t));
+		if (sz <= 0 || sz <= sizeof(image_header_t)) {
+			debug ("%s not found\n", aufile[i]);
+			continue;
+		}
+		if (au_check_cksum_valid(i, sz) < 0) {
+			debug ("%s checksum not valid\n", aufile[i]);
+			continue;
+		}
+		/* this is really not a good idea, but it's what the */
+		/* customer wants. */
+		cnt = 0;
+		got_ctrlc = 0;
+		do {
+			res = au_do_update(i, sz);
+			/* let the user break out of the loop */
+			if (ctrlc() || had_ctrlc()) {
+				clear_ctrlc();
+				if (res < 0)
+					got_ctrlc = 1;
+				break;
+			}
+			cnt++;
+#ifdef AU_TEST_ONLY
+		} while (res < 0 && cnt < 3);
+		if (cnt < 3)
+#else
+		} while (res < 0);
+#endif
+	}
+	usb_stop();
+	/* restore the old state */
+	disable_ctrlc(old_ctrlc);
+	return 0;
+}
+#endif /* CONFIG_AUTO_UPDATE */
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index 5d74bde..67969a6 100644
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -44,6 +44,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[];	/* FLASH chips info */
 
+extern int do_auto_update(void);
 ulong flash_get_size (ulong base, int banknum);
 
 #ifndef CFG_RAMBOOT
@@ -227,6 +228,10 @@ int misc_init_r (void)
 {
 	ulong flash_sup_end, snum;
 
+#ifdef CONFIG_AUTO_UPDATE
+	/* this has priority over all else */
+	do_auto_update();
+#endif
 	/*
 	 * Adjust flash start and offset to detected values
 	 */
diff --git a/board/nc650/nand.c b/board/nc650/nand.c
index de54386..6bb7c31 100644
--- a/board/nc650/nand.c
+++ b/board/nc650/nand.c
@@ -106,12 +106,13 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
  * Members with a "?" were not set in the merged testing-NAND branch,
  * so they are not set here either.
  */
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 
 	nand->hwcontrol = nc650_hwcontrol;
 	nand->eccmode = NAND_ECC_SOFT;
 	nand->chip_delay = 12;
 /*	nand->options = NAND_SAMSUNG_LP_OPTIONS;*/
+	return 0;
 }
 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
diff --git a/board/netstar/nand.c b/board/netstar/nand.c
index f470c1a..7852365 100644
--- a/board/netstar/nand.c
+++ b/board/netstar/nand.c
@@ -55,12 +55,13 @@ static int netstar_nand_ready(struct mtd_info *mtd)
 }
 ***/
 
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 	nand->options = NAND_SAMSUNG_LP_OPTIONS;
 	nand->eccmode = NAND_ECC_SOFT;
 	nand->hwcontrol = netstar_nand_hwcontrol;
 /*	nand->dev_ready = netstar_nand_ready; */
 	nand->chip_delay = 18;
+	return 0;
 }
 #endif
diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c
index 1931d64..92f9c01 100644
--- a/board/prodrive/pdnb3/nand.c
+++ b/board/prodrive/pdnb3/nand.c
@@ -148,7 +148,7 @@ static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
 	return 1;
 }
 
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 	pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE;
 
@@ -167,5 +167,6 @@ void board_nand_init(struct nand_chip *nand)
 	nand->read_buf   = pdnb3_nand_read_buf;
 	nand->verify_buf = pdnb3_nand_verify_buf;
 	nand->dev_ready  = pdnb3_nand_dev_ready;
+	return 0;
 }
 #endif
diff --git a/board/tqm8272/Makefile b/board/tqm8272/Makefile
new file mode 100644
index 0000000..3dbf913
--- /dev/null
+++ b/board/tqm8272/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/tqm8272/config.mk b/board/tqm8272/config.mk
new file mode 100644
index 0000000..af7a81e
--- /dev/null
+++ b/board/tqm8272/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TQM8272 boards
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/tqm8272/tqm8272.c b/board/tqm8272/tqm8272.c
new file mode 100644
index 0000000..8257c77
--- /dev/null
+++ b/board/tqm8272/tqm8272.c
@@ -0,0 +1,1234 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+#include <command.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/m8260_pci.h>
+#endif
+#if CONFIG_OF_FLAT_TREE
+#include <ft_build.h>
+#include <image.h>
+#endif
+
+#if 0
+#define deb_printf(fmt,arg...) \
+	printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
+#else
+#define deb_printf(fmt,arg...) \
+	do { } while (0)
+#endif
+
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+unsigned long board_get_cpu_clk_f (void);
+#endif
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 *ATMTXEN */
+	/* PA30 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTCA	*/
+	/* PA29 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTSOC	*/
+	/* PA28 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 *ATMRXEN */
+	/* PA27 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRSOC */
+	/* PA26 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRCA */
+	/* PA25 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[0] */
+	/* PA9	*/ {   1,   1,	 0,   1,   0,	0   }, /* SMC2 TXD */
+	/* PA8	*/ {   1,   1,	 0,   0,   0,	0   }, /* SMC2 RXD */
+	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
+	/* PA6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA6 */
+	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
+	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
+	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
+	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
+	/* PA1	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA1 */
+	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,	 0,   0,   0,	0   }, /* PB17 */
+	/* PB16 */ {   0,   0,	 0,   0,   0,	0   }, /* PB16 */
+	/* PB15 */ {   0,   0,	 0,   0,   0,	0   }, /* PB15 */
+	/* PB14 */ {   0,   0,	 0,   0,   0,	0   }, /* PB14 */
+	/* PB13 */ {   0,   0,	 0,   0,   0,	0   }, /* PB13 */
+	/* PB12 */ {   0,   0,	 0,   0,   0,	0   }, /* PB12 */
+	/* PB11 */ {   0,   0,	 0,   0,   0,	0   }, /* PB11 */
+	/* PB10 */ {   0,   0,	 0,   0,   0,	0   }, /* PB10 */
+	/* PB9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB9 */
+	/* PB8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB8 */
+	/* PB7	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB7 */
+	/* PB6	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB6 */
+	/* PB5	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB5 */
+	/* PB4	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB4 */
+	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
+	/* PC30 */ {   0,   0,	 0,   0,   0,	0   }, /* PC30 */
+	/* PC29 */ {   1,   1,	 1,   0,   0,	0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,	 0,   1,   0,	0   }, /* PC28 */
+	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* PC27 */
+	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
+	/* PC25 */ {   0,   0,	 0,   1,   0,	0   }, /* PC25 */
+	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
+	/* PC23 */ {   0,   1,	 0,   1,   0,	0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,	 0,   0,   0,	0   }, /* ATMRFCLK */
+	/* PC21 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   1,   0,	 0,   1,   0,	0   }, /* PC17 MDC */
+	/* PC16 */ {   1,   0,	 0,   0,   0,	0   }, /* PC16 MDIO*/
+	/* PC15 */ {   0,   0,	 0,   1,   0,	0   }, /* PC15 */
+	/* PC14 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
+	/* PC12 */ {   0,   0,	 0,   1,   0,	0   }, /* PC12 */
+	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* PC11 */
+	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* PC10 */
+	/* PC9	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC9 */
+	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
+	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
+	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
+	/* PC5	*/ {   1,   1,	 0,   1,   0,	0   }, /* PC5 SMC1 TXD */
+	/* PC4	*/ {   1,   1,	 0,   0,   0,	0   }, /* PC4 SMC1 RXD */
+	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
+	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
+	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
+	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,	 0,   1,   0,	0   }, /* PD28 */
+	/* PD27 */ {   0,   0,	 0,   1,   0,	0   }, /* PD27 */
+	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
+	/* PD25 */ {   0,   0,	 0,   1,   0,	0   }, /* PD25 */
+	/* PD24 */ {   0,   0,	 0,   1,   0,	0   }, /* PD24 */
+	/* PD23 */ {   0,   0,	 0,   1,   0,	0   }, /* PD23 */
+	/* PD22 */ {   0,   0,	 0,   1,   0,	0   }, /* PD22 */
+	/* PD21 */ {   0,   0,	 0,   1,   0,	0   }, /* PD21 */
+	/* PD20 */ {   0,   0,	 0,   1,   0,	0   }, /* PD20 */
+	/* PD19 */ {   0,   0,	 0,   1,   0,	0   }, /* PD19 */
+	/* PD18 */ {   0,   0,	 0,   1,   0,	0   }, /* PD19 */
+	/* PD17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXPRTY */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,	 1,   0,   1,	0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,	 1,   0,   1,	0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
+	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
+	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
+	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
+	/* PD9	*/ {   1,   1,	 0,   1,   0,	0   }, /* SMC1 TXD */
+	/* PD8	*/ {   1,   1,	 0,   0,   0,	0   }, /* SMC1 RXD */
+	/* PD7	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD7 */
+	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
+	/* PD5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PD5 */
+	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
+	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    }
+};
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/* UPM pattern for bus clock = 66.7 MHz */
+static const uint upmTable67[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
+    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
+    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 100 MHz */
+static const uint upmTable100[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
+    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
+    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 133.3 MHz */
+static const uint upmTable133[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
+    /* 0x04 */	0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
+    /* 0x1C */	0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+static int	chipsel = 0;
+
+/* UPM pattern for slow init */
+static const uint upmTableSlow[] =
+{
+    /* Offset	UPM Read Single RAM array entry */
+    /* 0x00 */	0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
+    /* 0x04 */	0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry */
+    /* 0x18 */	0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80,
+    /* 0x1C */	0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for fast init */
+static const uint upmTableFast[] =
+{
+    /* Offset	UPM Read Single RAM array entry */
+    /* 0x00 */	0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
+    /* 0x04 */	0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry */
+    /* 0x18 */	0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00,
+    /* 0x1C */	0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	char *p = (char *) HWIB_INFO_START_ADDR;
+
+	puts ("Board: ");
+	if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
+		puts (p);
+	} else {
+		puts ("No HWIB assuming TQM8272");
+	}
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+static int get_cas_latency (void)
+{
+	/* get it from the option -ts in CIB */
+	/* default is 3 */
+	int	ret = 3;
+	int	pos = 0;
+	char	*p = (char *) CIB_INFO_START_ADDR;
+
+	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
+		if (*p < ' ' || *p > '~') { /* ASCII strings! */
+			return ret;
+		}
+		if (*p == '-') {
+			if ((p[1] == 't') && (p[2] == 's')) {
+				return (p[4] - '0');
+			}
+		}
+		p++;
+		pos++;
+	}
+	return ret;
+}
+#endif
+
+static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col)
+{
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+	int	clk = board_get_cpu_clk_f ();
+	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	int	busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0);
+	int	cas;
+
+	sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \
+			 PSDMR_BUFCMD);
+	if (busmode) {
+		switch (clk) {
+			case 66666666:
+				sdmr |= (PSDMR_RFRC_66MHZ_60X | \
+					PSDMR_PRETOACT_66MHZ_60X | \
+					PSDMR_WRC_66MHZ_60X | \
+					PSDMR_BUFCMD_66MHZ_60X);
+				break;
+			case 100000000:
+				sdmr |= (PSDMR_RFRC_100MHZ_60X | \
+					PSDMR_PRETOACT_100MHZ_60X | \
+					PSDMR_WRC_100MHZ_60X | \
+					PSDMR_BUFCMD_100MHZ_60X);
+				break;
+
+		}
+	} else {
+		switch (clk) {
+			case 66666666:
+				sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \
+					PSDMR_PRETOACT_66MHZ_SINGLE | \
+					PSDMR_WRC_66MHZ_SINGLE | \
+					PSDMR_BUFCMD_66MHZ_SINGLE);
+				break;
+			case 100000000:
+				sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \
+					PSDMR_PRETOACT_100MHZ_SINGLE | \
+					PSDMR_WRC_100MHZ_SINGLE | \
+					PSDMR_BUFCMD_100MHZ_SINGLE);
+				break;
+			case 133333333:
+				sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \
+					PSDMR_PRETOACT_133MHZ_SINGLE | \
+					PSDMR_WRC_133MHZ_SINGLE | \
+					PSDMR_BUFCMD_133MHZ_SINGLE);
+				break;
+		}
+	}
+	cas = get_cas_latency();
+	sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK);
+	sdmr |= cas;
+	sdmr |= ((cas - 1) << 6);
+	return sdmr;
+#else
+	return sdmr;
+#endif
+}
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base, int col)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
+	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
+
+	*orx_ptr = orx;
+	sdmr = set_sdram_timing (sdmr_ptr, sdmr, col);
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	long size8, size9;
+#endif
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
+					  (uchar *) CFG_SDRAM_BASE, 8);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
+					  (uchar *) CFG_SDRAM_BASE, 9);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL - %ld MB, ", psize >> 20);
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
+						  (uchar *) CFG_SDRAM_BASE, 8);
+		printf ("(60x:8COL - %ld MB, ", psize >> 20);
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+
+static inline int scanChar (char *p, int len, unsigned long *number)
+{
+	int	akt = 0;
+
+	*number = 0;
+	while (akt < len) {
+		if ((*p >= '0') && (*p <= '9')) {
+			*number *= 10;
+			*number += *p - '0';
+			p += 1;
+		} else {
+			if (*p == '-')	return akt;
+			return -1;
+		}
+		akt ++;
+	}
+	return akt;
+}
+
+typedef struct{
+	int	Bus;
+	int	flash;
+	int	flash_nr;
+	int	ram;
+	int	ram_cs;
+	int	nand;
+	int	nand_cs;
+	int	eeprom;
+	int	can;
+	unsigned long	cpunr;
+	unsigned long	option;
+	int	SecEng;
+	int	cpucl;
+	int	cpmcl;
+	int	buscl;
+	int	busclk_real_ok;
+	int	busclk_real;
+	unsigned char	OK;
+	unsigned char  ethaddr[20];
+} HWIB_INFO;
+
+HWIB_INFO	hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
+			 0, 0, 0, 0, 0, 0};
+
+static int dump_hwib(void)
+{
+	HWIB_INFO	*hw = &hwinf;
+	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	char *s = getenv("serial#");
+
+	if (hw->OK) {
+		printf ("HWIB on %x\n", HWIB_INFO_START_ADDR);
+		printf ("serial : %s\n", s);
+		printf ("ethaddr: %s\n", hw->ethaddr);
+		printf ("FLASH	: %x nr:%d\n", hw->flash, hw->flash_nr);
+		printf ("RAM	: %x cs:%d\n", hw->ram, hw->ram_cs);
+		printf ("CPU	: %d\n", hw->cpunr);
+		printf ("CAN	: %d\n", hw->can);
+		if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom);
+		else printf ("No EEprom\n");
+		if (hw->nand) {
+			printf ("NAND	: %x\n", hw->nand);
+			printf ("NAND CS: %d\n", hw->nand_cs);
+		} else { printf ("No NAND\n");}
+		printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII"));
+		printf ("  real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \
+				 "60x" : "Single PQII"));
+		printf ("Option : %x\n", hw->option);
+		printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no"));
+		printf ("CPM Clk: %d\n", hw->cpmcl);
+		printf ("CPU Clk: %d\n", hw->cpucl);
+		printf ("Bus Clk: %d\n", hw->buscl);
+		if (hw->busclk_real_ok) {
+			printf ("  real Clk: %d\n", hw->busclk_real);
+		}
+		printf ("CAS	: %d\n", get_cas_latency());
+	} else {
+		printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR);
+	}
+	return 0;
+}
+
+static inline int search_real_busclk (int *clk)
+{
+	int	part = 0, pos = 0;
+	char *p = (char *) CIB_INFO_START_ADDR;
+	int	ok = 0;
+
+	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
+		if (*p < ' ' || *p > '~') { /* ASCII strings! */
+			return 0;
+		}
+		switch (part) {
+		default:
+			if (*p == '-') {
+				++part;
+			}
+			break;
+		case 3:
+			if (*p == '-') {
+				++part;
+				break;
+			}
+			if (*p == 'b') {
+				ok = 1;
+				p++;
+				break;
+			}
+			if (ok) {
+				switch (*p) {
+				case '6':
+					*clk = 66666666;
+					return 1;
+					break;
+				case '1':
+					if (p[1] == '3') {
+						*clk = 133333333;
+					} else {
+						*clk = 100000000;
+					}
+					return 1;
+					break;
+				}
+			}
+			break;
+		}
+		p++;
+	}
+	return 0;
+}
+
+int analyse_hwib (void)
+{
+	char	*p = (char *) HWIB_INFO_START_ADDR;
+	int	anz;
+	int	part = 1, i = 0, pos = 0;
+	HWIB_INFO	*hw = &hwinf;
+
+	deb_printf(" %s pointer: %p\n", __FUNCTION__, p);
+	/* Head = TQM */
+	if (*((unsigned long *)p) != (unsigned long)CFG_HWINFO_MAGIC) {
+		deb_printf("No HWIB\n");
+		return -1;
+	}
+	p += 3;
+	if (scanChar (p, 4, &hw->cpunr) < 0) {
+		deb_printf("No CPU\n");
+		return -2;
+	}
+	p +=4;
+
+	hw->flash = 0x200000 << (*p - 'A');
+	p++;
+	hw->flash_nr = *p - '0';
+	p++;
+
+	hw->ram = 0x2000000 << (*p - 'A');
+	p++;
+	if (*p == '2') {
+		hw->ram_cs = 2;
+		p++;
+	}
+
+	if (*p == 'A') hw->can = 1;
+	if (*p == 'B') hw->can = 2;
+	p +=1;
+	p +=1;	/* connector */
+	if (*p != '0') {
+		hw->eeprom = 0x100 << (*p - 'A');
+	}
+	p++;
+
+	if ((*p < '0') || (*p > '9')) {
+		/* NAND before z-option */
+		hw->nand = 0x8000000 << (*p - 'A');
+		p++;
+		hw->nand_cs = *p - '0';
+		p += 2;
+	}
+	/* z-option */
+	anz = scanChar (p, 4, &hw->option);
+	if (anz < 0) {
+		deb_printf("No option\n");
+		return -3;
+	}
+	if (hw->option & 0x8) hw->Bus = 1;
+	p += anz;
+	if (*p != '-') {
+		deb_printf("No -\n");
+		return -4;
+	}
+	p++;
+	/* C option */
+	if (*p == 'E') {
+		hw->SecEng = 1;
+		p++;
+	}
+	switch (*p) {
+		case 'M': hw->cpucl = 266666666;
+			break;
+		case 'P': hw->cpucl = 300000000;
+			break;
+		case 'T': hw->cpucl = 400000000;
+			break;
+		default:
+			deb_printf("No CPU Clk: %c\n", *p);
+			return -5;
+			break;
+	}
+	p++;
+	switch (*p) {
+		case 'I': hw->cpmcl = 200000000;
+			break;
+		case 'M': hw->cpmcl = 300000000;
+			break;
+		default:
+			deb_printf("No CPM Clk\n");
+			return -6;
+			break;
+	}
+	p++;
+	switch (*p) {
+		case 'B': hw->buscl = 66666666;
+			break;
+		case 'E': hw->buscl = 100000000;
+			break;
+		case 'F': hw->buscl = 133333333;
+			break;
+		default:
+			deb_printf("No BUS Clk\n");
+			return -7;
+			break;
+	}
+	p++;
+
+	hw->OK = 1;
+	/* search MAC Address */
+	while ((*p != '\0') && (pos < CFG_HWINFO_SIZE)) {
+		if (*p < ' ' || *p > '~') { /* ASCII strings! */
+			return 0;
+		}
+		switch (part) {
+		default:
+			if (*p == ' ') {
+				++part;
+				i = 0;
+			}
+			break;
+		case 3:			/* Copy MAC address */
+			if (*p == ' ') {
+				++part;
+				i = 0;
+				break;
+			}
+			hw->ethaddr[i++] = *p;
+			if ((i % 3) == 2)
+				hw->ethaddr[i++] = ':';
+			break;
+
+		}
+		p++;
+	}
+
+	hw->busclk_real_ok = search_real_busclk (&hw->busclk_real);
+	return 0;
+}
+
+#if defined(CONFIG_GET_CPU_STR_F)
+/* !! This routine runs from Flash */
+char get_cpu_str_f (char *buf)
+{
+	char *p = (char *) HWIB_INFO_START_ADDR;
+	int	i = 0;
+
+	buf[i++] = 'M';
+	buf[i++] = 'P';
+	buf[i++] = 'C';
+	if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
+		buf[i++] = *&p[3];
+		buf[i++] = *&p[4];
+		buf[i++] = *&p[5];
+		buf[i++] = *&p[6];
+	} else {
+		buf[i++] = '8';
+		buf[i++] = '2';
+		buf[i++] = '7';
+		buf[i++] = 'x';
+	}
+	buf[i++] = 0;
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+/* !! This routine runs from Flash */
+unsigned long board_get_cpu_clk_f (void)
+{
+	char *p = (char *) HWIB_INFO_START_ADDR;
+	int i = 0;
+
+	if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
+		if (search_real_busclk (&i))
+			return i;
+	}
+	return CONFIG_8260_CLKIN;
+}
+#endif
+
+#if CONFIG_BOARD_EARLY_INIT_R
+
+static int can_test (unsigned long off)
+{
+	volatile unsigned char	*base	= (unsigned char *) (CFG_CAN_BASE + off);
+
+	*(base + 0x17) = 'T';
+	*(base + 0x18) = 'Q';
+	*(base + 0x19) = 'M';
+	if ((*(base + 0x17) != 'T') ||
+	    (*(base + 0x18) != 'Q') ||
+	    (*(base + 0x19) != 'M')) {
+		return 0;
+	}
+	return 1;
+}
+
+static int can_config_one (unsigned long off)
+{
+	volatile unsigned char	*ctrl	= (unsigned char *) (CFG_CAN_BASE + off);
+	volatile unsigned char	*cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02);
+	volatile unsigned char	*clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f);
+	unsigned char temp;
+
+	*cpu_if = 0x45;
+	temp = *ctrl;
+	temp |= 0x40;
+	*ctrl	= temp;
+	*clkout = 0x20;
+	temp = *ctrl;
+	temp &= ~0x40;
+	*ctrl	= temp;
+	return 0;
+}
+
+static int can_config (void)
+{
+	int	ret = 0;
+	can_config_one (0);
+	if (hwinf.can == 2) {
+		can_config_one (0x100);
+	}
+	/* make Test if they really there */
+	ret += can_test (0);
+	ret += can_test (0x100);
+	return ret;
+}
+
+static int init_can (void)
+{
+	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+	int	count = 0;
+
+	if ((hwinf.OK) && (hwinf.can)) {
+		memctl->memc_or4 = CFG_CAN_OR;
+		memctl->memc_br4 = CFG_CAN_BR;
+		/* upm Init */
+		upmconfig (UPMC, (uint *) upmTableFast,
+			   sizeof (upmTableFast) / sizeof (uint));
+		memctl->memc_mcmr =	(MxMR_DSx_3_CYCL |
+					MxMR_GPL_x4DIS |
+					MxMR_RLFx_2X |
+					MxMR_WLFx_2X |
+					MxMR_OP_NORM);
+		/* can configure */
+		count = can_config ();
+		printf ("CAN:	%d @ %x\n", count, CFG_CAN_BASE);
+		if (hwinf.can != count) printf("!!! difference to HWIB\n");
+	} else {
+		printf ("CAN:	No\n");
+	}
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	analyse_hwib ();
+	init_can ();
+	return 0;
+}
+#endif
+
+int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	dump_hwib ();
+	return 0;
+}
+
+U_BOOT_CMD(
+	  hwib, 1,	1,	do_hwib_dump,
+	  "hwib	   - dump HWIB'\n",
+	  "\n"
+);
+
+#ifdef CFG_UPDATE_FLASH_SIZE
+static int get_flash_timing (void)
+{
+	/* get it from the option -tf in CIB */
+	/* default is 0x00000c84 */
+	int	ret = 0x00000c84;
+	int	pos = 0;
+	int	nr = 0;
+	char	*p = (char *) CIB_INFO_START_ADDR;
+
+	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
+		if (*p < ' ' || *p > '~') { /* ASCII strings! */
+			return ret;
+		}
+		if (*p == '-') {
+			if ((p[1] == 't') && (p[2] == 'f')) {
+				p += 6;
+				ret = 0;
+				while (nr < 8) {
+				if ((*p >= '0') && (*p <= '9')) {
+					ret *= 0x10;
+					ret += *p - '0';
+					p += 1;
+					nr ++;
+				} else if ((*p >= 'A') && (*p <= 'F')) {
+					ret *= 10;
+					ret += *p - '7';
+					p += 1;
+					nr ++;
+				} else {
+					if (nr < 8) return 0x00000c84;
+					return ret;
+				}
+				}
+			}
+		}
+		p++;
+		pos++;
+	}
+	return ret;
+}
+
+/* Update the Flash_Size and the Flash Timing */
+int update_flash_size (int flash_size)
+{
+	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+	unsigned long reg;
+	unsigned long tim;
+
+	/* I must use reg, otherwise the board hang */
+	reg = memctl->memc_or0;
+	reg &= ~ORxU_AM_MSK;
+	reg |= MEG_TO_AM(flash_size >> 20);
+	tim = get_flash_timing ();
+	reg &= ~0xfff;
+	reg |= (tim & 0xfff);
+	memctl->memc_or0 = reg;
+	return 0;
+}
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+static u8 hwctl = 0;
+
+static void upmnand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		hwctl |= 0x1;
+		break;
+	case NAND_CTL_CLRCLE:
+		hwctl &= ~0x1;
+		break;
+
+	case NAND_CTL_SETALE:
+		hwctl |= 0x2;
+		break;
+
+	case NAND_CTL_CLRALE:
+		hwctl &= ~0x2;
+		break;
+	}
+}
+
+static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+
+	if (hwctl & 0x1) {
+		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
+	} else if (hwctl & 0x2) {
+		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
+	} else {
+		WRITE_NAND(byte, base);
+	}
+}
+
+static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+
+	return READ_NAND(base);
+}
+
+static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
+{
+	/* constant delay (see also tR in the datasheet) */
+	udelay(12); \
+	return 1;
+}
+
+#ifndef CONFIG_NAND_SPL
+static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i< len; i++)
+		buf[i] = *base;
+}
+
+static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i< len; i++)
+		*base = buf[i];
+}
+
+static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i < len; i++)
+		if (buf[i] != *base)
+			return -1;
+	return 0;
+}
+#endif /* #ifndef CONFIG_NAND_SPL */
+
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+	chipsel = chip;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	static	int	UpmInit = 0;
+	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+
+	if (hwinf.nand == 0) return -1;
+
+	/* Setup the UPM */
+	if (UpmInit == 0) {
+		switch (hwinf.busclk_real) {
+		case 100000000:
+			upmconfig (UPMB, (uint *) upmTable100,
+			   sizeof (upmTable100) / sizeof (uint));
+			break;
+		case 133333333:
+			upmconfig (UPMB, (uint *) upmTable133,
+			   sizeof (upmTable133) / sizeof (uint));
+			break;
+		default:
+			upmconfig (UPMB, (uint *) upmTable67,
+			   sizeof (upmTable67) / sizeof (uint));
+			break;
+		}
+		UpmInit = 1;
+	}
+
+	/* Setup the memctrl */
+	memctl->memc_or3 = CFG_NAND_OR;
+	memctl->memc_br3 = CFG_NAND_BR;
+	memctl->memc_mbmr = (MxMR_OP_NORM);
+
+	nand->eccmode = NAND_ECC_SOFT;
+
+	nand->hwcontrol	 = upmnand_hwcontrol;
+	nand->read_byte	 = upmnand_read_byte;
+	nand->write_byte = upmnand_write_byte;
+	nand->dev_ready	 = tqm8272_dev_ready;
+
+#ifndef CONFIG_NAND_SPL
+	nand->write_buf	 = tqm8272_write_buf;
+	nand->read_buf	 = tqm8272_read_buf;
+	nand->verify_buf = tqm8272_verify_buf;
+#endif
+
+	/*
+	 * Select required NAND chip
+	 */
+	board_nand_select_device(nand, 0);
+	return 0;
+}
+
+#endif	/* CFG_CMD_NAND */
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+int board_early_init_f (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
+	return 0;
+}
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
diff --git a/board/tqm8272/u-boot.lds b/board/tqm8272/u-boot.lds
new file mode 100644
index 0000000..05f29c6
--- /dev/null
+++ b/board/tqm8272/u-boot.lds
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c
index 5d2cd65..a417143 100644
--- a/board/zylonite/nand.c
+++ b/board/zylonite/nand.c
@@ -448,7 +448,7 @@ static void dfc_gpio_init(void)
  * Members with a "?" were not set in the merged testing-NAND branch,
  * so they are not set here either.
  */
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 	unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
 
@@ -576,6 +576,7 @@ void board_nand_init(struct nand_chip *nand)
 	nand->cmdfunc = dfc_cmdfunc;
 	nand->autooob = &delta_oob;
 	nand->badblock_pattern = &delta_bbt_descr;
+	return 0;
 }
 
 #else