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| author | Ye.Li <B37916@freescale.com> | 2014-02-26 18:30:54 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-03-05 16:09:14 +0800 |
| commit | a116c531da6e7685e8c562ddbcdf8f8afb5b485e (patch) | |
| tree | 5141bca1ef31bce6bf95f83e28a1323f348b7d23 /board | |
| parent | f94e50c82f14136d95afa54c5539bf00c764594d (diff) | |
| download | u-boot-imx-a116c531da6e7685e8c562ddbcdf8f8afb5b485e.zip u-boot-imx-a116c531da6e7685e8c562ddbcdf8f8afb5b485e.tar.gz u-boot-imx-a116c531da6e7685e8c562ddbcdf8f8afb5b485e.tar.bz2 | |
ENGR00301441-2 iMX6SX/SL: Modify SOC to support two ENET
iMX6SX has different enet system clocks with iMX6SL, and has two ENET
controllers. So update clocks and soc APIs accordingly to support this
features.
1. Modify the clock API "enable_fec_clock" to enable enet system clock
for each enet controller.
2. Enet RGMII TX clock source may come from external or internal PLL.
By default, use the external phy CLK_25M output as TX clock source.
Add a configuration "CONFIG_FEC_CLOCK_FROM_ANATOP" for using internal
PLL
3. Add clock API "fec_set_rate" to set the RGMII clocks from internal PLL.
4. Modify the MAC address function "imx_get_mac_from_fuse" to get either
ENET MAC address.
5. Add clock API "enable_fec_25m_clock" to enable ENET 25Mhz reference clock.
6. Modify 17x17 arm2 BSP and imx6slevk BSP to fit the new APIs.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx6slevk/mx6slevk.c | 2 | ||||
| -rw-r--r-- | board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c | 7 |
2 files changed, 5 insertions, 4 deletions
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 33c82d9..68c100e 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -611,7 +611,7 @@ static int setup_fec(void) /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - ret = enable_fec_clock(); + ret = enable_fec_clock(0); if (ret) return ret; diff --git a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c index f78375b..38391ad 100644 --- a/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c +++ b/board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c @@ -248,7 +248,8 @@ int board_eth_init(bd_t *bis) setup_iomux_fec1(); - ret = cpu_eth_init(bis); + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); if (ret) printf("FEC1 MXC: %s:failed\n", __func__); @@ -271,12 +272,12 @@ static int setup_fec(void) clrbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); #endif - ret = enable_fec_clock(); + ret = enable_fec_clock(0); if (ret) return ret; #ifdef CONFIG_FEC_CLOCK_FROM_ANATOP - fec_set_rate(125000000); + fec_set_rate(0, 125000000); #endif #ifdef CONFIG_FEC_ENABLE_MAX7322 |