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authorEnric Balletbo i Serra <eballetbo@iseebcn.com>2013-09-10 11:12:26 +0200
committerTom Rini <trini@ti.com>2013-10-07 07:43:46 -0400
commit94b32f60fe8f21b60e8e1f31dcb27bcec7aa1fff (patch)
treed7397cda87620933cacdfa5c64ead897d634cabd /board
parente3cf9692053a4989f76a8964ab7d29df4fee90c0 (diff)
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ARM: IGEP0033: Update timing to run DDR at 400MHz.
We can run the DDR at 400MHz, so update the timings for that purpose. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Diffstat (limited to 'board')
-rw-r--r--board/isee/igep0033/board.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 9e91f68..a9c34c6 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -64,7 +64,7 @@ static struct emif_regs ddr3_emif_reg_data = {
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
- 303, OSC-1, 1, -1, -1, -1, -1};
+ 400, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params *get_dpll_ddr_params(void)
{
@@ -83,7 +83,7 @@ void set_mux_conf_regs(void)
void sdram_init(void)
{
- config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+ config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#endif