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| author | Fabio Estevam <fabio.estevam@nxp.com> | 2016-08-29 20:37:16 -0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-09-06 18:22:48 +0200 |
| commit | 7dbda25ecd6d7cba13d29161675309ca43e3ba12 (patch) | |
| tree | d4b74d4f5163b2a6d30d67314e32f56c113dfdd7 /board | |
| parent | edf0093732225c2fd0791c3864e9a3eef1f92f19 (diff) | |
| download | u-boot-imx-7dbda25ecd6d7cba13d29161675309ca43e3ba12.zip u-boot-imx-7dbda25ecd6d7cba13d29161675309ca43e3ba12.tar.gz u-boot-imx-7dbda25ecd6d7cba13d29161675309ca43e3ba12.tar.bz2 | |
mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang
When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk,
we observe a hang when going into the lowest operational point of cpufreq.
This hang issue does not happen on the NXP U-Boot version.
After comparing the SPL DDR initialization against the DCD table
from NXP U-Boot, the key difference that causes the hang is the
MDREF register setting:
DATA 4 0x021B0020 0x00000800
,which means:
REF_SEL = 0 --> Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes
So adjust the MDREF initialization for mx6ul_evk accordingly
to fix the kernel hang issue at low bus frequency.
Reported-by: Eric Nelson <eric@nelint.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 32953ae..126e499 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -804,8 +804,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = { .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ + .refsel = 0, /* Refresh cycles at 64KHz */ + .refr = 1, /* 2 refresh commands per refresh cycle */ }; static struct mx6_ddr3_cfg mem_ddr = { |