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authorPrafulla Wadaskar <prafulla@marvell.com>2010-03-03 15:27:37 +0530
committerTom Rix <Tom.Rix@windriver.com>2010-03-07 12:36:36 -0600
commit637833c2d669f9a370706e275e7103454c3c83ec (patch)
tree6fe9c2c17feb1f11020ca058d46a8b06ffdb66de /board
parente4d34492017c95e4041ea0c581e1ab8d1d49381b (diff)
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arm: kirkwood: suen3: fixed build warning
This patch fixes following build warning Invalid Kwbimage command Type - valid names are: BOOT_FROM, NAND_ECC_MODE, NAND_PAGE_SIZE, SATA_PIO_MODE, DDR_INIT_DELAY, DATA, , spi, nand, sata, pex, uart Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Diffstat (limited to 'board')
-rw-r--r--board/keymile/km_arm/kwbimage.cfg3
1 files changed, 1 insertions, 2 deletions
diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg
index d6edd27..26d6aa0 100644
--- a/board/keymile/km_arm/kwbimage.cfg
+++ b/board/keymile/km_arm/kwbimage.cfg
@@ -64,7 +64,6 @@ DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
# bit31-30: 01
DATA 0xFFD01404 0x36343000 # DDR Controller Control Low
- 0x38543000
# bit 3-0: 0 reserved
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
@@ -170,7 +169,7 @@ DATA 0xFFD0149C 0x0000E90F # CPU ODT Control
# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
+# bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0