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author | Tom Rini <trini@konsulko.com> | 2016-10-13 13:38:49 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2016-10-13 13:38:49 -0400 |
commit | 44afdc4a12b9f6f48338e7975e4f08cfe90dba74 (patch) | |
tree | 56b563576cc0986ce57a97d7c80a41391ca29417 /board | |
parent | c69f6d04ec66433f2360490a5cd0263c83aab18f (diff) | |
parent | c9abfbdd66ed97e1cac8553d0b31bd23f68480a9 (diff) | |
download | u-boot-imx-44afdc4a12b9f6f48338e7975e4f08cfe90dba74.zip u-boot-imx-44afdc4a12b9f6f48338e7975e4f08cfe90dba74.tar.gz u-boot-imx-44afdc4a12b9f6f48338e7975e4f08cfe90dba74.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-net
Diffstat (limited to 'board')
-rw-r--r-- | board/ti/am335x/board.c | 154 |
1 files changed, 121 insertions, 33 deletions
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 0ed16ca..fc1353a 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -47,11 +47,19 @@ DECLARE_GLOBAL_DATA_PTR; #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) +#define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11) +#define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26) -#if defined(CONFIG_SPL_BUILD) || \ - (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH)) static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -#endif + +#define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT) +#define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT) + +#define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1) +#define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1) + +#define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024) +#define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024) /* * Read header information from EEPROM into global structure. @@ -492,9 +500,9 @@ void sdram_init(void) } #endif -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ +#if !defined(CONFIG_SPL_BUILD) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) -static void request_and_set_gpio(int gpio, char *name) +static void request_and_set_gpio(int gpio, char *name, int val) { int ret; @@ -510,7 +518,7 @@ static void request_and_set_gpio(int gpio, char *name) goto err_free_gpio; } - gpio_set_value(gpio, 1); + gpio_set_value(gpio, val); return; @@ -518,7 +526,8 @@ err_free_gpio: gpio_free(gpio); } -#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N); +#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1); +#define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0); /** * RMII mode on ICEv2 board needs 50MHz clock. Given the clock @@ -548,20 +557,76 @@ int board_init(void) #if defined(CONFIG_NOR) || defined(CONFIG_NAND) gpmc_init(); #endif -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) - int rv; +#if !defined(CONFIG_SPL_BUILD) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (board_is_icev2()) { + int rv; + u32 reg; + REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); - REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL); + /* Make J19 status available on GPIO1_26 */ + REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL); + REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); + /* + * Both ports can be set as RMII-CPSW or MII-PRU-ETH using + * jumpers near the port. Read the jumper value and set + * the pinmux, external mux and PHY clock accordingly. + * As jumper line is overridden by PHY RX_DV pin immediately + * after bootstrap (power-up/reset), we need to sample + * it during PHY reset using GPIO rising edge detection. + */ REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); + /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */ + reg = readl(GPIO0_RISINGDETECT) | BIT(11); + writel(reg, GPIO0_RISINGDETECT); + reg = readl(GPIO1_RISINGDETECT) | BIT(26); + writel(reg, GPIO1_RISINGDETECT); + /* Reset PHYs to capture the Jumper setting */ + gpio_set_value(GPIO_PHY_RESET, 0); + udelay(2); /* PHY datasheet states 1uS min. */ + gpio_set_value(GPIO_PHY_RESET, 1); + + reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11); + if (reg) { + writel(reg, GPIO0_IRQSTATUS1); /* clear irq */ + /* RMII mode */ + printf("ETH0, CPSW\n"); + } else { + /* MII mode */ + printf("ETH0, PRU\n"); + cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */ + } + + reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26); + if (reg) { + writel(reg, GPIO1_IRQSTATUS1); /* clear irq */ + /* RMII mode */ + printf("ETH1, CPSW\n"); + gpio_set_value(GPIO_MUX_MII_CTRL, 1); + } else { + /* MII mode */ + printf("ETH1, PRU\n"); + cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */ + } + + /* disable rising edge IRQs */ + reg = readl(GPIO0_RISINGDETECT) & ~BIT(11); + writel(reg, GPIO0_RISINGDETECT); + reg = readl(GPIO1_RISINGDETECT) & ~BIT(26); + writel(reg, GPIO1_RISINGDETECT); rv = setup_clock_synthesizer(&cdce913_data); if (rv) { printf("Clock synthesizer setup failed %d\n", rv); return rv; } + + /* reset PHYs */ + gpio_set_value(GPIO_PHY_RESET, 0); + udelay(2); /* PHY datasheet states 1uS min. */ + gpio_set_value(GPIO_PHY_RESET, 1); } #endif @@ -571,6 +636,11 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { +#if !defined(CONFIG_SPL_BUILD) + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG int rc; char *name = NULL; @@ -584,6 +654,39 @@ int board_late_init(void) set_board_info_env(name); #endif +#if !defined(CONFIG_SPL_BUILD) + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (!getenv("eth1addr")) { + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } +#endif + return 0; } #endif @@ -652,11 +755,15 @@ static struct cpsw_platform_data cpsw_data = { int board_eth_init(bd_t *bis) { int rv, n = 0; +#if defined(CONFIG_USB_ETHER) && \ + (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; - __maybe_unused struct ti_am_eeprom *header; - /* try reading mac address from efuse */ + /* + * use efuse mac address for USB ethernet as we know that + * both CPSW and USB ethernet will never be active at the same time + */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; @@ -665,32 +772,13 @@ int board_eth_init(bd_t *bis) mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; +#endif + #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) - if (!getenv("ethaddr")) { - printf("<ethaddr> not set. Validating first E-fuse MAC\n"); - - if (is_valid_ethaddr(mac_addr)) - eth_setenv_enetaddr("ethaddr", mac_addr); - } #ifdef CONFIG_DRIVER_TI_CPSW - - mac_lo = readl(&cdev->macid1l); - mac_hi = readl(&cdev->macid1h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; - - if (!getenv("eth1addr")) { - if (is_valid_ethaddr(mac_addr)) - eth_setenv_enetaddr("eth1addr", mac_addr); - } - if (read_eeprom() < 0) puts("Could not get board ID.\n"); |