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authorNagabhushana Netagunte <nagabhushana.netagunte@ti.com>2011-09-03 22:21:04 -0400
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-09-04 11:36:19 +0200
commit0f3d6b06ea06e5b0295e4a8222a25bc95a70c026 (patch)
tree91a2566d7d9f01c2920e00042d77a7364e40fd28 /board
parentba511f779a584f77b4b798fc40685bfe8d3d5163 (diff)
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da850: modifications for Logic PD Rev.3 AM18xx EVM
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for NOR to work on Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but NOR flash will. Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'board')
-rw-r--r--board/davinci/da8xxevm/da850evm.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 8c3d64e..2f950e7 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -109,6 +109,8 @@ const struct pinmux_config nand_pins[] = {
#elif defined(CONFIG_USE_NOR)
/* NOR pin muxer settings */
const struct pinmux_config nor_pins[] = {
+ /* GP0[11] is required for NOR to work on Rev 3 EVMs */
+ { pinmux(0), 8, 4 }, /* GP0[11] */
{ pinmux(5), 1, 6 },
{ pinmux(6), 1, 6 },
{ pinmux(7), 1, 0 },
@@ -278,6 +280,7 @@ u32 get_board_rev(void)
int board_init(void)
{
+ u32 val;
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
@@ -325,6 +328,16 @@ int board_init(void)
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
+#ifdef CONFIG_USE_NOR
+ /* Set the GPIO direction as output */
+ clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
+
+ /* Set the output as low */
+ val = readl(GPIO_BANK0_REG_SET_ADDR);
+ val |= (0x01 << 11);
+ writel(val, GPIO_BANK0_REG_CLR_ADDR);
+#endif
+
#ifdef CONFIG_DRIVER_TI_EMAC
if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
return 1;