Merge branch 'master' of git://git.denx.de/u-boot-arm

16 files changed, 842 insertions, 301 deletions

diff --git a/board/Marvell/guruplug/Makefile b/board/Marvell/guruplug/Makefile
new file mode 100644
index 0000000..99748a7
--- /dev/null
+++ b/board/Marvell/guruplug/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= guruplug.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/guruplug/config.mk b/board/Marvell/guruplug/config.mk
new file mode 100644
index 0000000..caa26b6
--- /dev/null
+++ b/board/Marvell/guruplug/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x00600000
+
+KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
new file mode 100644
index 0000000..ba47ca1
--- /dev/null
+++ b/board/Marvell/guruplug/guruplug.c
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "guruplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(GURUPLUG_OE_VAL_LOW,
+			GURUPLUG_OE_VAL_HIGH,
+			GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,	/* GPIO_RST */
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GE1_8,
+		MPP29_GE1_9,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GE1_14,
+		MPP35_GE1_15,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_TDM_SPI_SCK,
+		MPP41_TDM_SPI_MISO,
+		MPP42_TDM_SPI_MOSI,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO, 	/* M_RLED */
+		MPP47_GPIO,	/* M_GLED */
+		MPP48_GPIO,	/* B_RLED */
+		MPP49_GPIO,	/* B_GLED */
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config);
+
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+	}
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void mv_phy_88e1121_init(char *name)
+{
+	u16 reg;
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__FUNCTION__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, &reg);
+	reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
+	miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
+
+	/* reset the phy */
+	if (miiphy_read (name, devadr, PHY_BMCR, &reg) != 0) {
+		printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
+		return;
+	}
+	if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) {
+		printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
+		return;
+	}
+
+	printf("88E1121 Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+	/* configure and initialize both PHY's */
+	mv_phy_88e1121_init("egiga0");
+	mv_phy_88e1121_init("egiga1");
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/guruplug/guruplug.h b/board/Marvell/guruplug/guruplug.h
new file mode 100644
index 0000000..5bc16b4
--- /dev/null
+++ b/board/Marvell/guruplug/guruplug.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __GURUPLUG_H
+#define __GURUPLUG_H
+
+#define GURUPLUG_OE_LOW		(~(0))
+#define GURUPLUG_OE_HIGH	(~(0))
+#define GURUPLUG_OE_VAL_LOW	0
+#define GURUPLUG_OE_VAL_HIGH	(0xf << 16) /* 4 LED Pins high */
+
+/* PHY related */
+#define MV88E1121_MAC_CTRL2_REG		21
+#define MV88E1121_PGADR_REG		22
+#define MV88E1121_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1121_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __GURUPLUG_H */
diff --git a/board/Marvell/guruplug/kwbimage.cfg b/board/Marvell/guruplug/kwbimage.cfg
new file mode 100644
index 0000000..2afd927
--- /dev/null
+++ b/board/Marvell/guruplug/kwbimage.cfg
@@ -0,0 +1,162 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b9b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc	#  DDR Address Control
+# bit1-0:   01, Cs0width=x8
+# bit3-2:   10, Cs0size=1Gb
+# bit5-4:   01, Cs1width=x8
+# bit7-6:   10, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/davedenx/qong/lowlevel_init.S b/board/davedenx/qong/lowlevel_init.S
index 198dd76..80bed92 100644
--- a/board/davedenx/qong/lowlevel_init.S
+++ b/board/davedenx/qong/lowlevel_init.S
@@ -42,6 +42,27 @@
 	bcs 1b
 .endm
 
+.macro SETUP_RAM cfg, ctl
+	/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+	REG	0xB8001010, 0x00000004
+	ldr r3, =\cfg
+	ldr r2, =WEIM_ESDCFG0
+	str r3, [r2]
+	REG	0xB8001000, 0x92100000
+	REG	0x80000f00, 0x12344321
+	REG	0xB8001000, 0xa2100000
+	REG	0x80000000, 0x12344321
+	REG	0x80000000, 0x12344321
+	REG	0xB8001000, 0xb2100000
+	REG8	0x80000033, 0xda
+	REG8	0x81000000, 0xff
+	ldr r3, =\ctl
+	ldr r2, =WEIM_ESDCTL0
+	str r3, [r2]
+	REG	0x80000000, 0xDEADBEEF
+	REG	0xB8001010, 0x0000000c
+
+.endm
 /* RedBoot: To support 133MHz DDR */
 .macro init_drive_strength
 	/*
@@ -130,43 +151,86 @@ lowlevel_init:
 	/* Default: 1, 4, 12, 1 */
 	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
 
-	/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
-	REG	0xB8001010, 0x00000004
-	REG	0xB8001004, ((3 << 21) | /* tXP */	\
-			     (0 << 20) | /* tWTR */	\
-			     (2 << 18) | /* tRP */	\
-			     (1 << 16) | /* tMRD */	\
-			     (0 << 15) | /* tWR */	\
-			     (5 << 12) | /* tRAS */	\
-			     (1 << 10) | /* tRRD */	\
-			     (3 << 8)  | /* tCAS */	\
-			     (2 << 4)  | /* tRCD */	\
-			     (7 << 0)    /* tRC */ )
-	REG	0xB8001000, 0x92100000
-	REG	0x80000f00, 0x12344321
-	REG	0xB8001000, 0xa2100000
-	REG	0x80000000, 0x12344321
-	REG	0x80000000, 0x12344321
-	REG	0xB8001000, 0xb2100000
-	REG8	0x80000033, 0xda
-	REG8	0x81000000, 0xff
-	REG	0xB8001000, ((1 << 31) |				\
-			     (0 << 28) |				\
-			     (0 << 27) |				\
-			     (3 << 24) | /* 14 rows */			\
-			     (2 << 20) | /* 10 cols */			\
-			     (2 << 16) |				\
-			     (4 << 13) | /* 3.91us (64ms/16384) */	\
-			     (0 << 10) |				\
-			     (0 << 8)  |				\
-			     (1 << 7)  |				\
-			     (0 << 0))
-	REG	0x80000000, 0xDEADBEEF
-	REG	0xB8001010, 0x0000000c
+check_ddr_module:
+/* Set stackpointer in internal RAM to call get_ram_size */
+	ldr	sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16)
+	stmfd	sp!, {r0-r11, ip, lr}
+	mov	ip, lr		/* save link reg across call */
+
+	ldr	r0,=0x08000000
+	SETUP_RAM	ESDCFG0_256MB, ESDCTL0_256MB
+	ldr	r0,=0x80000000
+	ldr	r1,=0x10000000
+	bl	get_ram_size
+	ldr	r1,=0x10000000
+	cmp	r0,r1
+	beq	restore_regs
+	SETUP_RAM	ESDCFG0_128MB, ESDCTL0_128MB
+	ldr	r0,=0x80000000
+	ldr	r1,=0x08000000
+	bl	get_ram_size
+	ldr	r1,=0x08000000
+	cmp	r0,r1
+	beq	restore_regs
+
+restore_regs:
+	ldmfd	sp!, {r0-r11, ip, lr}
+	mov	lr, ip		/* restore link reg */
 
 	mov	pc, lr
 
+
 MPCTL_PARAM_399:
 	.word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
 UPCTL_PARAM_240:
 	.word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3  << 0))
+
+	.equ	ESDCFG0_128MB, \
+		(0 << 21) + /* tXP */ \
+		(1 << 20) + /* tWTR */ \
+		(2 << 18) + /* tRP */ \
+		(1 << 16) + /* tMRD */ \
+		(0 << 15) + /* tWR */ \
+		(5 << 12) + /* tRAS */ \
+		(1 << 10) + /* tRRD */ \
+		(3 << 8) + /* tCAS */ \
+		(2 << 4) + /* tRCD */ \
+		(0x0F << 0) /* tRC */
+
+	.equ	ESDCTL0_128MB, \
+		(1 << 31)  +	/* enable */ \
+		(0 << 28)  +	/* mode */ \
+		(0 << 27)  +	/* supervisor protect */ \
+		(2 << 24)  +	/* 13 rows */ \
+		(2 << 20)  +	/* 10 cols */ \
+		(2 << 16)  +	/* 32 bit */ \
+		(3 << 13)  +	/* 7.81us (64ms/8192) */ \
+		(0 << 10)  +	/* power down timer */ \
+		(0 << 8)  +	/* full page */ \
+		(1 << 7)  +	/* burst length */ \
+		(0 << 0)	/* precharge timer */
+
+	.equ	ESDCFG0_256MB, \
+		(3 << 21)  + 	/* tXP */ \
+		(0 << 20)  + 	/* tWTR */ \
+		(2 << 18)  + 	/* tRP */ \
+		(1 << 16)  + 	/* tMRD */ \
+		(0 << 15)  + 	/* tWR */ \
+		(5 << 12)  + 	/* tRAS */ \
+		(1 << 10)  + 	/* tRRD */ \
+		(3 << 8)   + 	/* tCAS */ \
+		(2 << 4)   +	/* tRCD */ \
+		(7 << 0)	/* tRC */
+
+	.equ	ESDCTL0_256MB, \
+		(1 << 31)  + \
+		(0 << 28)  + \
+		(0 << 27)  + \
+		(3 << 24)  + /* 14 rows */ \
+		(2 << 20)  + /* 10 cols */ \
+		(2 << 16)  + \
+		(4 << 13)  + /* 3.91us (64ms/16384) */ \
+		(0 << 10)  + \
+		(0 << 8)   + \
+		(1 << 7)   + \
+		(0 << 0)
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index b801150..eb9218e 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -25,6 +25,7 @@
 #include <netdev.h>
 #include <asm/arch/mx31.h>
 #include <asm/arch/mx31-regs.h>
+#include <nand.h>
 #include "qong_fpga.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -38,6 +39,15 @@ int dram_init (void)
 	return 0;
 }
 
+static void qong_fpga_reset(void)
+{
+	mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
+	udelay(30);
+	mx31_gpio_set(QONG_FPGA_RST_PIN, 1);
+
+	udelay(300);
+}
+
 int board_init (void)
 {
 	/* Chip selects */
@@ -101,6 +111,15 @@ int board_init (void)
 	mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
 	mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
 	mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
+
+	/* FPGA reset  Pin */
+	/* rstn = 0 */
+	mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
+	mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT);
+
+	/* set interrupt pin as input */
+	mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN);
+
 #endif
 
 	/* setup pins for UART1 */
@@ -118,7 +137,7 @@ int board_init (void)
 
 int checkboard (void)
 {
-	printf("Board: DAVE/DENX QongEVB-LITE\n");
+	printf("Board: DAVE/DENX Qong\n");
 	return 0;
 }
 
@@ -127,32 +146,11 @@ int misc_init_r (void)
 #ifdef CONFIG_QONG_FPGA
 	u32 tmp;
 
-	/* FPGA reset */
-	/* rstn = 0 */
-	tmp = __REG(GPIO2_BASE + GPIO_DR);
-	tmp &= (~(1 << QONG_FPGA_RST_PIN));
-	__REG(GPIO2_BASE + GPIO_DR) = tmp;
-	/* set the GPIO as output */
-	tmp = __REG(GPIO2_BASE + GPIO_GDIR);
-	tmp |= (1 << QONG_FPGA_RST_PIN);
-	__REG(GPIO2_BASE + GPIO_GDIR) = tmp;
-	/* wait */
-	udelay(30);
-	/* rstn = 1 */
-	tmp = __REG(GPIO2_BASE + GPIO_DR);
-	tmp |= (1 << QONG_FPGA_RST_PIN);
-	__REG(GPIO2_BASE + GPIO_DR) = tmp;
-	/* set interrupt pin as input */
-	__REG(GPIO2_BASE + GPIO_GDIR) = tmp | (1 << QONG_FPGA_IRQ_PIN);
-	/* wait while the FPGA starts */
-	udelay(300);
-
 	tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
 	printf("FPGA:  ");
 	printf("version register = %u.%u.%u\n",
 		(tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
 #endif
-
 	return 0;
 }
 
@@ -164,3 +162,56 @@ int board_eth_init(bd_t *bis)
 	return 0;
 #endif
 }
+
+#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
+static void board_nand_setup(void)
+{
+
+	/* CS3: NAND 8-bit */
+	__REG(CSCR_U(3)) = 0x00004f00;
+	__REG(CSCR_L(3)) = 0x20013b31;
+	__REG(CSCR_A(3)) = 0x00020800;
+	__REG(IOMUXC_GPR) |= 1 << 13;
+
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
+
+	/* Make sure to reset the fpga else you cannot access NAND */
+	qong_fpga_reset();
+
+	/* Enable NAND flash */
+	mx31_gpio_set(15, 1);
+	mx31_gpio_set(14, 1);
+	mx31_gpio_direction(15, MX31_GPIO_DIRECTION_OUT);
+	mx31_gpio_direction(16, MX31_GPIO_DIRECTION_IN);
+	mx31_gpio_direction(14, MX31_GPIO_DIRECTION_IN);
+	mx31_gpio_set(15, 0);
+
+}
+
+int qong_nand_rdy(void *chip)
+{
+	udelay(1);
+	return mx31_gpio_get(16);
+}
+
+void qong_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+	if (chip >= 0)
+		mx31_gpio_set(15, 0);
+	else
+		mx31_gpio_set(15, 1);
+
+}
+
+void qong_nand_plat_init(void *chip)
+{
+	struct nand_chip *nand = (struct nand_chip *)chip;
+	nand->chip_delay = 20;
+	nand->select_chip = qong_nand_select_chip;
+	nand->options &= ~NAND_BUSWIDTH_16;
+	board_nand_setup();
+}
+
+#endif
diff --git a/board/davedenx/qong/qong_fpga.h b/board/davedenx/qong/qong_fpga.h
index e8042b1..4e11f5a 100644
--- a/board/davedenx/qong/qong_fpga.h
+++ b/board/davedenx/qong/qong_fpga.h
@@ -33,8 +33,8 @@
 #define	QONG_FPGA_TMS_PIN		25
 #define	QONG_FPGA_TDI_PIN		8
 #define	QONG_FPGA_TDO_PIN		7
-#define	QONG_FPGA_RST_PIN		16
-#define	QONG_FPGA_IRQ_PIN		8
+#define	QONG_FPGA_RST_PIN		48
+#define	QONG_FPGA_IRQ_PIN		40
 #endif
 
 #endif /* QONG_FPGA_H */
diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg
index db09913..a875e8f 100644
--- a/board/freescale/mx51evk/imximage.cfg
+++ b/board/freescale/mx51evk/imximage.cfg
@@ -26,7 +26,7 @@
 # The syntax is taken as close as possible with the kwbimage
 
 # Boot Device : one of
-# spi_flash, nand, onenand, sd_card
+# spi, sd (the board has no nand neither onenand)
 
 BOOT_FROM	spi
 
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 8754563..f0b7abc 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -72,72 +72,6 @@ static void setup_iomux_uart(void)
 	mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
 }
 
-static void setup_expio(void)
-{
-	u32 reg;
-	struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
-	struct clkctl *pclkctl = (struct clkctl *)CCM_BASE_ADDR;
-
-	/* CS5 setup */
-	mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
-	writel(0x00410089, &pweim[5].csgcr1);
-	writel(0x00000002, &pweim[5].csgcr2);
-
-	/* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
-	writel(0x32260000, &pweim[5].csrcr1);
-
-	/* APR = 0 */
-	writel(0x00000000, &pweim[5].csrcr2);
-
-	/*
-	 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
-	 * WCSA=0, WCSN=0
-	 */
-	writel(0x72080F00, &pweim[5].cswcr1);
-
-	mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR +
-						IO_BOARD_OFFSET);
-	if ((readw(&mx51_io_board->id1) == 0xAAAA) &&
-		(readw(&mx51_io_board->id2) == 0x5555)) {
-		if (is_soc_rev(CHIP_REV_2_0) < 0) {
-			reg = readl(&pclkctl->cbcdr);
-			reg = (reg & (~0x70000)) | 0x30000;
-			writel(reg, &pclkctl->cbcdr);
-			/* make sure divider effective */
-			while (readl(&pclkctl->cdhipr) != 0)
-				;
-			writel(0x0, &pclkctl->ccdr);
-		}
-	} else {
-		/* CS1 */
-		writel(0x00410089, &pweim[1].csgcr1);
-		writel(0x00000002, &pweim[1].csgcr2);
-		/*  RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
-		writel(0x32260000, &pweim[1].csrcr1);
-		/* APR=0 */
-		writel(0x00000000, &pweim[1].csrcr2);
-		/*
-		 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
-		 * WEN=0, WCSA=0, WCSN=0
-		 */
-		writel(0x72080F00, &pweim[1].cswcr1);
-		mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR +
-						IO_BOARD_OFFSET);
-	}
-
-	/* Reset interrupt status reg */
-	writew(0x1F, &(mx51_io_board->int_rest));
-	writew(0x00, &(mx51_io_board->int_rest));
-	writew(0xFFFF, &(mx51_io_board->int_mask));
-
-	/* Reset the XUART and Ethernet controllers */
-	reg = readw(&(mx51_io_board->sw_reset));
-	reg |= 0x9;
-	writew(reg, &(mx51_io_board->sw_reset));
-	reg &= ~0x9;
-	writew(reg, &(mx51_io_board->sw_reset));
-}
-
 static void setup_iomux_fec(void)
 {
 	/*FEC_MDIO*/
@@ -349,7 +283,6 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
 	setup_iomux_uart();
-	setup_expio();
 	setup_iomux_fec();
 	return 0;
 }
diff --git a/board/freescale/mx51evk/mx51evk.h b/board/freescale/mx51evk/mx51evk.h
index 524cdcc..2854e71 100644
--- a/board/freescale/mx51evk/mx51evk.h
+++ b/board/freescale/mx51evk/mx51evk.h
@@ -47,5 +47,4 @@ struct io_board_ctrl {
 };
 #endif
 
-#define IO_BOARD_OFFSET		(0x20000)
 #endif
diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c
index 63375d5..4427415 100644
--- a/board/logicpd/imx27lite/imx27lite.c
+++ b/board/logicpd/imx27lite/imx27lite.c
@@ -29,6 +29,10 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_init (void)
 {
 	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+#if defined(CONFIG_SYS_NAND_LARGEPAGE)
+	struct system_control_regs *sc_regs =
+		(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+#endif
 
 	gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@@ -43,9 +47,20 @@ int board_init (void)
 				&regs->port[PORTC].dr);
 #endif
 #ifdef CONFIG_MXC_MMC
+#if defined(CONFIG_MAGNESIUM)
+	mx27_sd1_init_pins();
+#else
 	mx27_sd2_init_pins();
 #endif
+#endif
 
+#if defined(CONFIG_SYS_NAND_LARGEPAGE)
+	/*
+	 * set in FMCR NF_FMS Bit(5) to 1
+	 * (NAND Flash with 2 Kbyte page size)
+	 */
+	writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr);
+#endif
 	return 0;
 }
 
@@ -68,6 +83,7 @@ int dram_init (void)
 
 int checkboard(void)
 {
-	printf("LogicPD imx27lite\n");
+	puts ("Board: ");
+	puts(CONFIG_BOARDNAME);
 	return 0;
 }
diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c
index 396c3e7..ff21ce6 100644
--- a/board/ronetix/pm9261/led.c
+++ b/board/ronetix/pm9261/led.c
@@ -26,19 +26,21 @@
 #include <common.h>
 #include <asm/arch/at91sam9261.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
 #include <asm/arch/io.h>
 
 void coloured_LED_init(void)
 {
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+	writel(1 << AT91SAM9261_ID_PIOC, &pmc->pcer);
 
-	at91_set_gpio_output(CONFIG_RED_LED, 1);
-	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
-	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+	at91_set_pio_output(CONFIG_RED_LED, 1);
+	at91_set_pio_output(CONFIG_GREEN_LED, 1);
+	at91_set_pio_output(CONFIG_YELLOW_LED, 1);
 
-	at91_set_gpio_value(CONFIG_RED_LED, 0);
-	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+	at91_set_pio_value(CONFIG_RED_LED, 0);
+	at91_set_pio_value(CONFIG_GREEN_LED, 1);
+	at91_set_pio_value(CONFIG_YELLOW_LED, 1);
 }
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index 8662339..53d8c48 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -27,13 +27,14 @@
 #include <common.h>
 #include <asm/sizes.h>
 #include <asm/arch/at91sam9261.h>
-#include <asm/arch/at91sam9261_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
 #include <asm/arch/io.h>
 #include <asm/arch/hardware.h>
 #include <lcd.h>
@@ -55,39 +56,48 @@ DECLARE_GLOBAL_DATA_PTR;
 static void pm9261_nand_hw_init(void)
 {
 	unsigned long csa;
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC_BASE;
+	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
 	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBICSA);
-	at91_sys_write(AT91_MATRIX_EBICSA,
-		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+	csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-	at91_sys_write(AT91_SMC_MODE(3),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
-		       AT91_SMC_DBW_16 |
+		AT91_SMC_MODE_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
-		       AT91_SMC_DBW_8 |
+		AT91_SMC_MODE_DBW_8 |
 #endif
-		       AT91_SMC_TDF_(2));
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
+
+	writel(1 << AT91SAM9261_ID_PIOA |
+		1 << AT91SAM9261_ID_PIOC,
+		&pmc->pcer);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(AT91_PIN_PA16, 1);
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(AT91_PIN_PC14, 1);
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 
-	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
-	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* NANDOE */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* NANDWE */
 }
 #endif
 
@@ -95,23 +105,30 @@ static void pm9261_nand_hw_init(void)
 #ifdef CONFIG_DRIVER_DM9000
 static void pm9261_dm9000_hw_init(void)
 {
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
 	/* Configure SMC CS2 for DM9000 */
-	at91_sys_write(AT91_SMC_SETUP(2),
-		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(2),
-		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
-		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
-	at91_sys_write(AT91_SMC_CYCLE(2),
-		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
-	at91_sys_write(AT91_SMC_MODE(2),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
-		       AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
-		       AT91_SMC_TDF_(1));
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[2].setup);
+
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
+		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
+		&smc->cs[2].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
+		&smc->cs[2].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+		AT91_SMC_MODE_TDF_CYCLE(1),
+		&smc->cs[2].mode);
 
 	/* Configure Interrupt pin as input, no pull-up */
-	at91_set_gpio_input(AT91_PIN_PA24, 0);
+	writel(1 << AT91SAM9261_ID_PIOA, &pmc->pcer);
+	at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
 }
 #endif
 
@@ -135,40 +152,42 @@ vidinfo_t panel_info = {
 
 void lcd_enable(void)
 {
-	at91_set_gpio_value(AT91_PIN_PA22, 0);  /* power up */
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);  /* power up */
 }
 
 void lcd_disable(void)
 {
-	at91_set_gpio_value(AT91_PIN_PA22, 1);  /* power down */
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 1);  /* power down */
 }
 
 static void pm9261_lcd_hw_init(void)
 {
-	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
-	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
-	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
-	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
-	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
-	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
-	at91_set_A_periph(AT91_PIN_PB9, 0);	/* LCDD4 */
-	at91_set_A_periph(AT91_PIN_PB10, 0);	/* LCDD5 */
-	at91_set_A_periph(AT91_PIN_PB11, 0);	/* LCDD6 */
-	at91_set_A_periph(AT91_PIN_PB12, 0);	/* LCDD7 */
-	at91_set_A_periph(AT91_PIN_PB15, 0);	/* LCDD10 */
-	at91_set_A_periph(AT91_PIN_PB16, 0);	/* LCDD11 */
-	at91_set_A_periph(AT91_PIN_PB17, 0);	/* LCDD12 */
-	at91_set_A_periph(AT91_PIN_PB18, 0);	/* LCDD13 */
-	at91_set_A_periph(AT91_PIN_PB19, 0);	/* LCDD14 */
-	at91_set_A_periph(AT91_PIN_PB20, 0);	/* LCDD15 */
-	at91_set_B_periph(AT91_PIN_PB23, 0);	/* LCDD18 */
-	at91_set_B_periph(AT91_PIN_PB24, 0);	/* LCDD19 */
-	at91_set_B_periph(AT91_PIN_PB25, 0);	/* LCDD20 */
-	at91_set_B_periph(AT91_PIN_PB26, 0);	/* LCDD21 */
-	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
-	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */
-
-	at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* LCDDEN */
+	at91_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* LCDCC */
+	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTB, 10, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* LCDD12 */
+	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTB, 19, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTB, 20, 0);	/* LCDD15 */
+	at91_set_b_periph(AT91_PIO_PORTB, 23, 0);	/* LCDD18 */
+	at91_set_b_periph(AT91_PIO_PORTB, 24, 0);	/* LCDD19 */
+	at91_set_b_periph(AT91_PIO_PORTB, 25, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTB, 26, 0);	/* LCDD21 */
+	at91_set_b_periph(AT91_PIO_PORTB, 27, 0);	/* LCDD22 */
+	at91_set_b_periph(AT91_PIO_PORTB, 28, 0);	/* LCDD23 */
+
+	writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
 
 	gd->fb_base = AT91SAM9261_SRAM_BASE;
 }
@@ -222,11 +241,14 @@ void lcd_show_board_info(void)
 
 int board_init(void)
 {
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
 	/* Enable Ctrlc */
 	console_init_f();
 
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+	writel(1 << AT91SAM9261_ID_PIOA |
+		1 << AT91SAM9261_ID_PIOC,
+		&pmc->pcer);
 
 	/* arch number of PM9261-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PM9261;
diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c
index fe1a1d2..4e585a4 100644
--- a/board/ronetix/pm9263/led.c
+++ b/board/ronetix/pm9263/led.c
@@ -26,18 +26,19 @@
 #include <common.h>
 #include <asm/arch/at91sam9263.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
 #include <asm/arch/io.h>
 
 void coloured_LED_init(void)
 {
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB |
-				      1 << AT91SAM9263_ID_PIOCDE);
+	writel(1 << AT91SAM9263_ID_PIOB, &pmc->pcer);
 
-	at91_set_gpio_output(CONFIG_RED_LED, 1);
-	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_pio_output(CONFIG_RED_LED, 1);
+	at91_set_pio_output(CONFIG_GREEN_LED, 1);
 
-	at91_set_gpio_value(CONFIG_RED_LED, 0);
-	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	at91_set_pio_value(CONFIG_RED_LED, 0);
+	at91_set_pio_value(CONFIG_GREEN_LED, 1);
 }
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 23ea154..c7835de 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -27,13 +27,13 @@
 #include <common.h>
 #include <asm/sizes.h>
 #include <asm/arch/at91sam9263.h>
-#include <asm/arch/at91sam9263_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
 #include <asm/arch/hardware.h>
 #include <lcd.h>
@@ -55,52 +55,59 @@ DECLARE_GLOBAL_DATA_PTR;
 static void pm9263_nand_hw_init(void)
 {
 	unsigned long csa;
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC0_BASE;
+	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
 
 	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
-	at91_sys_write(AT91_MATRIX_EBI0CSA,
-		       csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(1) |
-		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(1));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-	at91_sys_write(AT91_SMC_MODE(3),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
-		       AT91_SMC_DBW_16 |
+		AT91_SMC_MODE_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
-		       AT91_SMC_DBW_8 |
+		AT91_SMC_MODE_DBW_8 |
 #endif
-		       AT91_SMC_TDF_(2));
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
 #ifdef CONFIG_MACB
 static void pm9263_macb_hw_init(void)
 {
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pio_t	*pio	= (at91_pio_t *) AT91_PIO_BASE;
+
 	/*
 	 * PB27 enables the 50MHz oscillator for Ethernet PHY
 	 * 1 - enable
 	 * 0 - disable
 	 */
-	at91_set_gpio_output(AT91_PIN_PB27, 1);
-	at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
+	at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
+	at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
 
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+	writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
 
 	/*
 	 * Disable pull-up on:
@@ -110,19 +117,15 @@ static void pm9263_macb_hw_init(void)
 	 *
 	 * PHY has internal pull-down
 	 */
-	writel(pin_to_mask(AT91_PIN_PC25),
-	       pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
-	writel(pin_to_mask(AT91_PIN_PE25) |
-	       pin_to_mask(AT91_PIN_PE26),
-	       pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
 
+	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
 
 	/* Re-enable pull-up */
-	writel(pin_to_mask(AT91_PIN_PC25),
-	       pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
-	writel(pin_to_mask(AT91_PIN_PE25) |
-	       pin_to_mask(AT91_PIN_PE26),
-	       pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
+	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
 
 	at91_macb_hw_init();
 }
@@ -148,17 +151,17 @@ vidinfo_t panel_info = {
 
 void lcd_enable(void)
 {
-	at91_set_gpio_value(AT91_PIN_PA22, 1); /* power up */
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
 }
 
 void lcd_disable(void)
 {
-	at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
 }
 
 #ifdef CONFIG_LCD_IN_PSRAM
 
-#define PSRAM_CRE_PIN	AT91_PIN_PB29
+#define PSRAM_CRE_PIN	AT91_PIO_PORTB, 29
 #define PSRAM_CTRL_REG	(PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
 
 /* Initialize the PSRAM memory */
@@ -166,31 +169,34 @@ static int pm9263_lcd_hw_psram_init(void)
 {
 	volatile uint16_t x;
 	unsigned long csa;
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC1_BASE;
+	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
 
 	/* Enable CS3  3.3v, no pull-ups */
-	csa = at91_sys_read(AT91_MATRIX_EBI1CSA);
-	at91_sys_write(AT91_MATRIX_EBI1CSA,
-		       csa | AT91_MATRIX_EBI1_DBPUC |
-		       AT91_MATRIX_EBI1_VDDIOMSEL_3_3V);
+	csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
+		AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
+
+	writel(csa, &matrix->csa[1]);
 
 	/* Configure SMC1 CS0 for PSRAM - 16-bit */
-	at91_sys_write(AT91_SMC1_SETUP(0),
-		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC1_PULSE(0),
-		       AT91_SMC_NWEPULSE_(7) | AT91_SMC_NCS_WRPULSE_(7) |
-		       AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(7));
-	at91_sys_write(AT91_SMC1_CYCLE(0),
-		       AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
-	at91_sys_write(AT91_SMC1_MODE(0),
-		       AT91_SMC_DBW_16 |
-		       AT91_SMC_PMEN |
-		       AT91_SMC_PS_32);
+	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[0].setup);
+
+	writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
+		AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
+		&smc->cs[0].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+		&smc->cs[0].cycle);
+
+	writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
+		&smc->cs[0].mode);
 
 	/* setup PB29 as output */
-	at91_set_gpio_output(PSRAM_CRE_PIN, 1);
+	at91_set_pio_output(PSRAM_CRE_PIN, 1);
 
-	at91_set_gpio_value(PSRAM_CRE_PIN, 0);	/* set PSRAM_CRE_PIN to '0' */
+	at91_set_pio_value(PSRAM_CRE_PIN, 0);	/* set PSRAM_CRE_PIN to '0' */
 
 	/* PSRAM: write BCR */
 	x = readw(PSRAM_CTRL_REG);
@@ -216,7 +222,7 @@ static int pm9263_lcd_hw_psram_init(void)
 	/* test if the chip is MT45W2M16B */
 	if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
 		/* try with CRE=1 (MT45W2M16A) */
-		at91_set_gpio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
+		at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
 
 		/* write RCR of the PSRAM */
 		x = readw(PSRAM_CTRL_REG);
@@ -229,17 +235,14 @@ static int pm9263_lcd_hw_psram_init(void)
 		writew(0x1234, PHYS_PSRAM);
 		writew(0x5678, PHYS_PSRAM+2);
 		if ((readw(PHYS_PSRAM) != 0x1234)
-		   || (readw(PHYS_PSRAM + 2) != 0x5678))
+		  || (readw(PHYS_PSRAM + 2) != 0x5678))
 			return 1;
 
 	}
 
 	/* Bus matrix */
-	at91_sys_write( AT91_MATRIX_PRAS5, AT91_MATRIX_M5PR );
-	at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY |
-				(AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) |
-				AT91_MATRIX_DEFMSTR_TYPE_FIXED |
-				(AT91_MATRIX_SLOT_CYCLE & (0xFF << 0)));
+	writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
+	writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
 
 	return 0;
 }
@@ -247,35 +250,37 @@ static int pm9263_lcd_hw_psram_init(void)
 
 static void pm9263_lcd_hw_init(void)
 {
-	at91_set_A_periph(AT91_PIN_PC0, 0);	/* LCDVSYNC */
-	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
-	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
-	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
-	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
-	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
-	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
-	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
-	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
-	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
-	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
-	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
-	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
-	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
-	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD13 */
-	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
-	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
-	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
-	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
-	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
-	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD21 */
-	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
-	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */
-
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
+	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
+	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
+
+	writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
 
 	/* Power Control */
-	at91_set_gpio_output(AT91_PIN_PA22, 1);
-	at91_set_gpio_value(AT91_PIN_PA22, 0);	/* power down */
+	at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
+	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);	/* power down */
 
 #ifdef CONFIG_LCD_IN_PSRAM
 	/* initialize te PSRAM */
@@ -337,13 +342,15 @@ void lcd_show_board_info(void)
 
 int board_init(void)
 {
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
 	/* Enable Ctrlc */
 	console_init_f();
 
-	at91_sys_write(AT91_PMC_PCER,
-					(1 << AT91SAM9263_ID_PIOA) |
-					(1 << AT91SAM9263_ID_PIOCDE) |
-					(1 << AT91SAM9263_ID_PIOB));
+	writel((1 << AT91SAM9263_ID_PIOA) |
+		(1 << AT91SAM9263_ID_PIOCDE) |
+		(1 << AT91SAM9263_ID_PIOB),
+		&pmc->pcer);
 
 	/* arch number of AT91SAM9263EK-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PM9263;
@@ -394,7 +401,7 @@ int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
 #ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x01);
+	rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01);
 #endif
 	return rc;
 }