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authorRicardo Ribalda Delgado <ricardo.ribalda@gmail.com>2016-01-26 11:24:15 +0100
committerMichal Simek <michal.simek@xilinx.com>2016-01-27 15:55:32 +0100
commit6a2c1aaae7de22b4892ba0a12159bec346f87f0d (patch)
treed093d39b81e82d3b2980953bc6f34c16ace063aa /board/xilinx
parentad7321da8e5c56613b604cb91e064fbaa44b3283 (diff)
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ppc: xilinx-ppc4xx-generic: Update xparameters.h
-Remove UART address (It is now part of the dts). -Include dummy ns16550 clock -Fix address to last test Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'board/xilinx')
-rw-r--r--board/xilinx/ppc405-generic/xparameters.h6
-rw-r--r--board/xilinx/ppc440-generic/xparameters.h10
2 files changed, 8 insertions, 8 deletions
diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h
index e610407..90fe969 100644
--- a/board/xilinx/ppc405-generic/xparameters.h
+++ b/board/xilinx/ppc405-generic/xparameters.h
@@ -14,12 +14,12 @@
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_SPI_0_BASEADDR 0x83400000
-#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
-#define XPAR_UARTLITE_0_BAUDRATE 9600
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
+#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#endif
diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h
index 3c135ec..e307de9 100644
--- a/board/xilinx/ppc440-generic/xparameters.h
+++ b/board/xilinx/ppc440-generic/xparameters.h
@@ -12,12 +12,12 @@
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
-#define XPAR_INTC_0_BASEADDR 0x81800000
-#define XPAR_UARTLITE_0_BASEADDR 0x84000000
-#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
+#define XPAR_INTC_0_BASEADDR 0x87000000
+#define XPAR_FLASH_MEM0_BASEADDR 0xF0000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
-#define XPAR_UARTLITE_0_BAUDRATE 9600
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
+#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#endif