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authorBhuvanchandra DV <bhuvanchandra.dv@toradex.com>2015-06-01 18:37:17 +0530
committerStefano Babic <sbabic@denx.de>2015-06-08 08:41:55 +0200
commita7b1808ee3e87608bf740f845b6de6ebb550a339 (patch)
tree2368c5ccfe14a7006a573b65fc769e139455e950 /board/toradex/colibri_vf
parentd348a943e77ed72dd809cecf03365552545382b2 (diff)
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colibri_vf: Add pinmux entries for GPIOs
Inorder to use the pins as GPIO, apart from setting the alt-function, pinmuxing need to be done, this patch adds pinmux entries of few GPIOs. Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Diffstat (limited to 'board/toradex/colibri_vf')
-rw-r--r--board/toradex/colibri_vf/colibri_vf.c60
1 files changed, 60 insertions, 0 deletions
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index 31ebb19..e354c6d 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -146,6 +146,62 @@ static void setup_iomux_nfc(void)
}
#endif
+#ifdef CONFIG_VYBRID_GPIO
+static void setup_iomux_gpio(void)
+{
+ static const iomux_v3_cfg_t gpio_pads[] = {
+ VF610_PAD_PTA17__GPIO_7,
+ VF610_PAD_PTA20__GPIO_10,
+ VF610_PAD_PTA21__GPIO_11,
+ VF610_PAD_PTA30__GPIO_20,
+ VF610_PAD_PTA31__GPIO_21,
+ VF610_PAD_PTB0__GPIO_22,
+ VF610_PAD_PTB1__GPIO_23,
+ VF610_PAD_PTB6__GPIO_28,
+ VF610_PAD_PTB7__GPIO_29,
+ VF610_PAD_PTB8__GPIO_30,
+ VF610_PAD_PTB9__GPIO_31,
+ VF610_PAD_PTB12__GPIO_34,
+ VF610_PAD_PTB13__GPIO_35,
+ VF610_PAD_PTB16__GPIO_38,
+ VF610_PAD_PTB17__GPIO_39,
+ VF610_PAD_PTB18__GPIO_40,
+ VF610_PAD_PTB21__GPIO_43,
+ VF610_PAD_PTB22__GPIO_44,
+ VF610_PAD_PTC0__GPIO_45,
+ VF610_PAD_PTC1__GPIO_46,
+ VF610_PAD_PTC2__GPIO_47,
+ VF610_PAD_PTC3__GPIO_48,
+ VF610_PAD_PTC4__GPIO_49,
+ VF610_PAD_PTC5__GPIO_50,
+ VF610_PAD_PTC6__GPIO_51,
+ VF610_PAD_PTC7__GPIO_52,
+ VF610_PAD_PTC8__GPIO_53,
+ VF610_PAD_PTD31__GPIO_63,
+ VF610_PAD_PTD30__GPIO_64,
+ VF610_PAD_PTD29__GPIO_65,
+ VF610_PAD_PTD28__GPIO_66,
+ VF610_PAD_PTD27__GPIO_67,
+ VF610_PAD_PTD26__GPIO_68,
+ VF610_PAD_PTD25__GPIO_69,
+ VF610_PAD_PTD24__GPIO_70,
+ VF610_PAD_PTD9__GPIO_88,
+ VF610_PAD_PTD10__GPIO_89,
+ VF610_PAD_PTD11__GPIO_90,
+ VF610_PAD_PTD12__GPIO_91,
+ VF610_PAD_PTD13__GPIO_92,
+ VF610_PAD_PTB23__GPIO_93,
+ VF610_PAD_PTB26__GPIO_96,
+ VF610_PAD_PTB28__GPIO_98,
+ VF610_PAD_PTC29__GPIO_102,
+ VF610_PAD_PTC30__GPIO_103,
+ VF610_PAD_PTA7__GPIO_134,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+}
+#endif
+
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{ESDHC1_BASE_ADDR},
@@ -304,6 +360,10 @@ int board_early_init_f(void)
setup_iomux_nfc();
#endif
+#ifdef CONFIG_VYBRID_GPIO
+ setup_iomux_gpio();
+#endif
+
return 0;
}