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authorTom Rini <trini@ti.com>2011-11-18 12:48:06 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-12-06 23:59:38 +0100
commit9ae0d550741db45e933dc73e7135d1861e3a9b62 (patch)
treeb640b1a6600c6b7716ac922037e8f908e2126937 /board/timll/devkit8000
parentfc41ba1e2b4271bef197bfbf89d49458368319ce (diff)
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OMAP3 SPL: Rework memory initalization and devkit8000 support
This changes to making the board be responsible for providing the memory initialization timings in SPL and converts the devkit8000 to this framework. In SPL we try and initialize both CS0 and CS1. Cc: Frederik Kriewitz <frederik@kriewitz.eu> Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/timll/devkit8000')
-rw-r--r--board/timll/devkit8000/devkit8000.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index fee0dff..b06aab6 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -138,3 +138,24 @@ int board_eth_init(bd_t *bis)
return dm9000_initialize(bis);
}
#endif
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank. This
+ * provides the timing values back to the function that configures
+ * the memory. We have either one or two banks of 128MB DDR.
+ */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
+ u32 *mr)
+{
+ /* General SDRC config */
+ *mcfg = MICRON_V_MCFG_165(128 << 20);
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+ /* AC timings */
+ *ctrla = MICRON_V_ACTIMA_165;
+ *ctrlb = MICRON_V_ACTIMB_165;
+
+ *mr = MICRON_V_MR_165;
+}