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authorStefano Babic <sbabic@denx.de>2016-12-16 09:53:52 +0100
committerStefano Babic <sbabic@denx.de>2016-12-16 09:53:52 +0100
commitf2465934b46235287e07473fa4919035ba1a2b68 (patch)
treece6d4480a31d592dfee52222b620329a9c75b055 /board/ti
parent51efabac487d832632f9797a94ed2ba6fe98e718 (diff)
parent53e8ca22538c2cec691fe74098684a359302688c (diff)
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Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'board/ti')
-rw-r--r--board/ti/am335x/board.c15
-rw-r--r--board/ti/am335x/board.h13
-rw-r--r--board/ti/am57xx/board.c16
-rw-r--r--board/ti/common/board_detect.c10
4 files changed, 50 insertions, 4 deletions
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 111ed35..8eaf3e9 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -109,6 +109,16 @@ static const struct emif_regs ddr2_emif_reg_data = {
.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
};
+static const struct emif_regs ddr2_evm_emif_reg_data = {
+ .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+ .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+ .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+ .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+ .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+ .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
+ .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J128MJT125_RD_DQS,
.datawdsratio0 = MT41J128MJT125_WR_DQS,
@@ -198,6 +208,7 @@ static struct emif_regs ddr3_beagleblack_emif_reg_data = {
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
@@ -208,6 +219,7 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
+ .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
.zq_config = MT41J512M8RH125_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
PHY_EN_DYN_PWRDN,
@@ -486,6 +498,9 @@ void sdram_init(void)
config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
&ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
0);
+ else if (board_is_gp_evm())
+ config_ddr(266, &ioregs, &ddr2_data,
+ &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
else
config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index 9776df7..48c139a 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -11,6 +11,19 @@
#ifndef _BOARD_H_
#define _BOARD_H_
+/**
+ * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and
+ * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame
+ * Synchronization Lost errors. The values are the biggest that work
+ * reliably with offered video modes and the memory subsystem on the
+ * boards. These register have are briefly documented in "7.3.3.5.2
+ * Command Starvation" section of AM335x TRM. The REG_COS_COUNT_1 and
+ * REG_COS_COUNT_2 do not have any effect on current versions of
+ * AM335x.
+ */
+#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414
+#define EMIF_OCP_CONFIG_AM335X_EVM 0x003d3d3d
+
static inline int board_is_bone(void)
{
return board_ti_is("A335BONE");
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 797d7a4..5f2d4df 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -55,6 +55,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define SYSINFO_BOARD_NAME_MAX_LEN 45
+#define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
+#define TPS65903X_PAD2_POWERHOLD_MASK 0x20
+
const struct omap_sysinfo sysinfo = {
"Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
};
@@ -457,6 +460,7 @@ int board_init(void)
int board_late_init(void)
{
setup_board_eeprom_env();
+ u8 val;
/*
* DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
@@ -471,6 +475,18 @@ int board_late_init(void)
if (get_device_type() == HS_DEVICE)
setenv("boot_fit", "1");
+ /*
+ * Set the GPIO7 Pad to POWERHOLD. This has higher priority
+ * over DEV_CTRL.DEV_ON bit. This can be reset in case of
+ * PMIC Power off. So to be on the safer side set it back
+ * to POWERHOLD mode irrespective of the current state.
+ */
+ palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
+ &val);
+ val = val | TPS65903X_PAD2_POWERHOLD_MASK;
+ palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
+ val);
+
return 0;
}
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index 6e7ca91..a5dba94 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -123,8 +123,10 @@ int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
struct ti_common_eeprom *ep;
ep = TI_EEPROM_DATA;
+#ifndef CONFIG_SPL_BUILD
if (ep->header == TI_EEPROM_HEADER_MAGIC)
- goto already_read;
+ return 0; /* EEPROM has already been read */
+#endif
/* Initialize with a known bad marker for i2c fails.. */
ep->header = TI_DEAD_EEPROM_MAGIC;
@@ -157,7 +159,6 @@ int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
memcpy(ep->mac_addr, am_ep.mac_addr,
TI_EEPROM_HDR_NO_OF_MAC_ADDR * TI_EEPROM_HDR_ETH_ALEN);
-already_read:
return 0;
}
@@ -168,8 +169,10 @@ int __maybe_unused ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr)
struct ti_common_eeprom *ep;
ep = TI_EEPROM_DATA;
+#ifndef CONFIG_SPL_BUILD
if (ep->header == DRA7_EEPROM_HEADER_MAGIC)
- goto already_read;
+ return 0; /* EEPROM has already been read */
+#endif
/* Initialize with a known bad marker for i2c fails.. */
ep->header = TI_DEAD_EEPROM_MAGIC;
@@ -202,7 +205,6 @@ int __maybe_unused ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr)
strlcpy(ep->config, dra7_ep.config, TI_EEPROM_HDR_CONFIG_LEN + 1);
ti_eeprom_string_cleanup(ep->config);
-already_read:
return 0;
}