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authorMatt Porter <mporter@ti.com>2013-03-20 05:38:14 +0000
committerTom Rini <trini@ti.com>2013-05-10 08:25:54 -0400
commitcd87464d0873d2db920e6b712ef34e9c83cfe5e6 (patch)
tree057a3eaf119d541708b0aea9371a2d805839195a /board/ti/ti814x/mux.c
parentf485c8a35b38356a473208bec5ed786792c1eafe (diff)
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ti814x_evm: enable CPSW support
Adds CPSW support to the TI814X EVM configured with an ET1011C PHY in GMII mode. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/ti/ti814x/mux.c')
-rw-r--r--board/ti/ti814x/mux.c35
1 files changed, 35 insertions, 0 deletions
diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c
index 137acb4..fd9f364 100644
--- a/board/ti/ti814x/mux.c
+++ b/board/ti/ti814x/mux.c
@@ -40,6 +40,36 @@ static struct module_pin_mux mmc1_pin_mux[] = {
{-1},
};
+static struct module_pin_mux enet_pin_mux[] = {
+ {OFFSET(pincntl232), MODE(0x01)}, /* EMAC_RMREFCLK */
+ {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)}, /* MDCLK */
+ {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)}, /* MDIO */
+ {OFFSET(pincntl235), MODE(0x01)}, /* EMAC[0]_MTCLK */
+ {OFFSET(pincntl236), MODE(0x01)}, /* EMAC[0]_MCOL */
+ {OFFSET(pincntl237), MODE(0x01)}, /* EMAC[0]_MCRS */
+ {OFFSET(pincntl238), MODE(0x01)}, /* EMAC[0]_MRXER */
+ {OFFSET(pincntl239), MODE(0x01)}, /* EMAC[0]_MRCLK */
+ {OFFSET(pincntl240), MODE(0x01)}, /* EMAC[0]_MRXD[0] */
+ {OFFSET(pincntl241), MODE(0x01)}, /* EMAC[0]_MRXD[1] */
+ {OFFSET(pincntl242), MODE(0x01)}, /* EMAC[0]_MRXD[2] */
+ {OFFSET(pincntl243), MODE(0x01)}, /* EMAC[0]_MRXD[3] */
+ {OFFSET(pincntl244), MODE(0x01)}, /* EMAC[0]_MRXD[4] */
+ {OFFSET(pincntl245), MODE(0x01)}, /* EMAC[0]_MRXD[5] */
+ {OFFSET(pincntl246), MODE(0x01)}, /* EMAC[0]_MRXD[6] */
+ {OFFSET(pincntl247), MODE(0x01)}, /* EMAC[0]_MRXD[7] */
+ {OFFSET(pincntl248), MODE(0x01)}, /* EMAC[0]_MRXDV */
+ {OFFSET(pincntl249), MODE(0x01)}, /* EMAC[0]_GMTCLK */
+ {OFFSET(pincntl250), MODE(0x01)}, /* EMAC[0]_MTXD[0] */
+ {OFFSET(pincntl251), MODE(0x01)}, /* EMAC[0]_MTXD[1] */
+ {OFFSET(pincntl252), MODE(0x01)}, /* EMAC[0]_MTXD[2] */
+ {OFFSET(pincntl253), MODE(0x01)}, /* EMAC[0]_MTXD[3] */
+ {OFFSET(pincntl254), MODE(0x01)}, /* EMAC[0]_MTXD[4] */
+ {OFFSET(pincntl255), MODE(0x01)}, /* EMAC[0]_MTXD[5] */
+ {OFFSET(pincntl256), MODE(0x01)}, /* EMAC[0]_MTXD[6] */
+ {OFFSET(pincntl257), MODE(0x01)}, /* EMAC[0]_MTXD[7] */
+ {OFFSET(pincntl258), MODE(0x01)}, /* EMAC[0]_MTXEN */
+};
+
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
@@ -49,3 +79,8 @@ void enable_mmc1_pin_mux(void)
{
configure_module_pin_mux(mmc1_pin_mux);
}
+
+void enable_enet_pin_mux(void)
+{
+ configure_module_pin_mux(enet_pin_mux);
+}