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authorChin Liang See <clsee@altera.com>2016-09-21 10:26:04 +0800
committerMarek Vasut <marex@denx.de>2016-10-27 08:03:12 +0200
commitbdef7876adf74dea6178f2143705bc41262c7b06 (patch)
treebf7186c26acdd0e71077bd1ac68d338f9e3f3fdd /board/terasic
parent13022d852d5c233894fabb62279a2ae9e0355638 (diff)
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arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'board/terasic')
-rw-r--r--board/terasic/sockit/qts/sdram_config.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h
index 769aa77..9906436 100644
--- a/board/terasic/sockit/qts/sdram_config.h
+++ b/board/terasic/sockit/qts/sdram_config.h
@@ -49,6 +49,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF