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authorSoeren Moch <smoch@web.de>2015-01-23 19:03:37 +0100
committerStefano Babic <sbabic@denx.de>2015-02-23 09:11:37 +0100
commit5df3d19b1925ea63075664878fad84eeef28ea3e (patch)
tree0abc873980aa5ac7d489410bd1e05ab268b3c8a4 /board/tbs
parentd9f43c8f5c1d7ed27c99a06be85a4bb64b2c73fb (diff)
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board: tbs2910: Gate clock when switching async clock muxes
According to the i.MX6Q Reference Manual, clocks must be gated when switching input clocks of async clock muxes. So use clock gates. Avoid ldb_di0_ipu clock, because there is no clock gate for this signal. There have never been any complaints about problems with the old code, but the new approach is in line with the recommendations in the manual. Signed-off-by: Soeren Moch <smoch@web.de>
Diffstat (limited to 'board/tbs')
-rw-r--r--board/tbs/tbs2910/tbs2910.c28
1 files changed, 16 insertions, 12 deletions
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index dfa430e..42b166d 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -326,21 +326,25 @@ static void setup_display(void)
reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
writel(reg, &ccm->analog_pll_video);
- /* select video pll for ldb_di0_clk */
- reg = readl(&ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
- writel(reg, &ccm->cs2cdr);
+ /* gate ipu1_di0_clk */
+ reg = readl(&ccm->CCGR3);
+ reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &ccm->CCGR3);
- /* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */
- reg = readl(&ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
- writel(reg, &ccm->cscmr2);
-
- /* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */
+ /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
reg = readl(&ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
+ MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+ reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
+ (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
+ (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &ccm->chsccdr);
+
+ /* enable ipu1_di0_clk */
+ reg = readl(&ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &ccm->CCGR3);
}
#endif /* CONFIG_VIDEO_IPUV3 */