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| author | Ye.Li <B37916@freescale.com> | 2014-06-12 16:28:38 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-06-17 11:14:01 +0800 |
| commit | bfc7a914724643beb327d6b9412afa468ead81ec (patch) | |
| tree | 72abf6b9434d5e83c2f80ebf784fe7814e663f4e /board/solidrun | |
| parent | d94fe28bb7687a7e062865f36b812cfa73b9dfc8 (diff) | |
| download | u-boot-imx-bfc7a914724643beb327d6b9412afa468ead81ec.zip u-boot-imx-bfc7a914724643beb327d6b9412afa468ead81ec.tar.gz u-boot-imx-bfc7a914724643beb327d6b9412afa468ead81ec.tar.bz2 | |
ENGR00315894-65 iMX6SX:SABRESD Add RDC settings to BSP
According to the SRS, in the M4 CAN demo, the GPIO group1 will be
shared between A9 and M4. At A9 side, the pins 0, 1, 2, 3 are used.
M4 also uses one pin in its application.
To synchronize the registers setttings of GPIO1, must enable RDC
and RDC semaphore on the GPIO1.
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'board/solidrun')
0 files changed, 0 insertions, 0 deletions