Merge branch 'master' of git://git.denx.de/u-boot-arm

4 files changed, 850 insertions, 0 deletions

diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile
new file mode 100644
index 0000000..a09b467
--- /dev/null
+++ b/board/siemens/rut/Makefile
@@ -0,0 +1,49 @@
+#
+# Makefile
+#
+# (C) Copyright 2013 Siemens Schweiz AG
+# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# Based on:
+# u-boot:/board/ti/am335x/Makefile
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS	:= mux.o
+endif
+
+COBJS	+= board.o
+ifndef CONFIG_SPL_BUILD
+COBJS += ../common/factoryset.o
+endif
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
new file mode 100644
index 0000000..f2b0476
--- /dev/null
+++ b/board/siemens/rut/board.c
@@ -0,0 +1,432 @@
+/*
+ * Board functions for TI AM335X based rut board
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/board.c
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spi.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <video.h>
+#include <watchdog.h>
+#include "board.h"
+#include "../common/factoryset.h"
+#include "../../../drivers/video/da8xx-fb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+static void board_init_ddr(void)
+{
+struct emif_regs rut_ddr3_emif_reg_data = {
+	.sdram_config = 0x61C04AB2,
+	.sdram_tim1 = 0x0888A39B,
+	.sdram_tim2 = 0x26337FDA,
+	.sdram_tim3 = 0x501F830F,
+	.emif_ddr_phy_ctlr_1 = 0x6,
+	.zq_config = 0x50074BE4,
+	.ref_ctrl = 0x93B,
+};
+
+struct ddr_data rut_ddr3_data = {
+	.datardsratio0 = 0x3b,
+	.datawdsratio0 = 0x85,
+	.datafwsratio0 = 0x100,
+	.datawrsratio0 = 0xc1,
+	.datauserank0delay = 1,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+struct cmd_control rut_ddr3_cmd_ctrl_data = {
+	.cmd0csratio = 0x40,
+	.cmd0dldiff = 0,
+	.cmd0iclkout = 1,
+	.cmd1csratio = 0x40,
+	.cmd1dldiff = 0,
+	.cmd1iclkout = 1,
+	.cmd2csratio = 0x40,
+	.cmd2dldiff = 0,
+	.cmd2iclkout = 1,
+};
+
+	config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
+		   &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
+}
+
+static void spl_siemens_board_init(void)
+{
+	return;
+}
+#endif /* if def CONFIG_SPL_BUILD */
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_id		= 1,
+		.phy_if		= PHY_INTERFACE_MODE_RMII,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_id		= 0,
+		.phy_if		= PHY_INTERFACE_MODE_RMII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+int board_eth_init(bd_t *bis)
+{
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+	int n = 0;
+	int rv;
+
+#ifndef CONFIG_SPL_BUILD
+	factoryset_setenv();
+#endif
+
+	/* Set rgmii mode and enable rmii clock to be sourced from chip */
+	writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+	return n;
+}
+#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+
+#if defined(CONFIG_HW_WATCHDOG)
+static bool hw_watchdog_init_done;
+static int  hw_watchdog_trigger_level;
+
+void hw_watchdog_reset(void)
+{
+	if (!hw_watchdog_init_done)
+		return;
+
+	hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
+	gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
+}
+
+void hw_watchdog_init(void)
+{
+	gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
+	gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
+
+	hw_watchdog_reset();
+
+	hw_watchdog_init_done = 1;
+}
+#endif /* defined(CONFIG_HW_WATCHDOG) */
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+static struct da8xx_panel lcd_panels[] = {
+	/* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
+	[0] = {
+		.name   = "KWH043MC17-F01",
+		.width  = 480,
+		.height = 800,
+		.hfp = 50,              /* no spec, "don't care" values */
+		.hbp = 50,
+		.hsw = 50,
+		.vfp = 50,
+		.vbp = 50,
+		.vsw = 50,
+		.pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
+		.invert_pxl_clk = 1,
+	},
+	/* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
+	[1] = {
+		.name   = "KWH043ST20-F01",
+		.width  = 480,
+		.height = 800,
+		.hfp = 50,              /* no spec, "don't care" values */
+		.hbp = 50,
+		.hsw = 50,
+		.vfp = 50,
+		.vbp = 50,
+		.vsw = 50,
+		.pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
+		.invert_pxl_clk = 1,
+	},
+	/* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
+	[2] = {
+		.name   = "MI0430VT-1",
+		.width  = 480,
+		.height = 800,
+		.hfp = 50,              /* no spec, "don't care" values */
+		.hbp = 50,
+		.hsw = 50,
+		.vfp = 50,
+		.vbp = 50,
+		.vsw = 50,
+		.pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
+		.invert_pxl_clk = 1,
+	},
+};
+
+static const struct display_panel disp_panels[] = {
+	[0] = {
+		WVGA,
+		16,	/* RGB 888 */
+		16,
+		COLOR_ACTIVE,
+	},
+	[1] = {
+		WVGA,
+		16,	/* RGB 888 */
+		16,
+		COLOR_ACTIVE,
+	},
+	[2] = {
+		WVGA,
+		24,	/* RGB 888 */
+		16,
+		COLOR_ACTIVE,
+	},
+};
+
+static const struct lcd_ctrl_config lcd_cfgs[] = {
+	[0] = {
+		&disp_panels[0],
+		.ac_bias		= 255,
+		.ac_bias_intrpt		= 0,
+		.dma_burst_sz		= 16,
+		.bpp			= 16,
+		.fdd			= 0x80,
+		.tft_alt_mode		= 0,
+		.stn_565_mode		= 0,
+		.mono_8bit_mode		= 0,
+		.invert_line_clock	= 1,
+		.invert_frm_clock	= 1,
+		.sync_edge		= 0,
+		.sync_ctrl		= 1,
+		.raster_order		= 0,
+	},
+	[1] = {
+		&disp_panels[1],
+		.ac_bias		= 255,
+		.ac_bias_intrpt		= 0,
+		.dma_burst_sz		= 16,
+		.bpp			= 16,
+		.fdd			= 0x80,
+		.tft_alt_mode		= 0,
+		.stn_565_mode		= 0,
+		.mono_8bit_mode		= 0,
+		.invert_line_clock	= 1,
+		.invert_frm_clock	= 1,
+		.sync_edge		= 0,
+		.sync_ctrl		= 1,
+		.raster_order		= 0,
+	},
+	[2] = {
+		&disp_panels[2],
+		.ac_bias		= 255,
+		.ac_bias_intrpt		= 0,
+		.dma_burst_sz		= 16,
+		.bpp			= 24,
+		.fdd			= 0x80,
+		.tft_alt_mode		= 0,
+		.stn_565_mode		= 0,
+		.mono_8bit_mode		= 0,
+		.invert_line_clock	= 1,
+		.invert_frm_clock	= 1,
+		.sync_edge		= 0,
+		.sync_ctrl		= 1,
+		.raster_order		= 0,
+	},
+
+};
+
+/* no console on this board */
+int board_cfb_skip(void)
+{
+	return 1;
+}
+
+#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
+#define PLL_GET_N(v) (v & 0x7f)
+
+static struct dpll_regs dpll_lcd_regs = {
+	.cm_clkmode_dpll = CM_WKUP + 0x98,
+	.cm_idlest_dpll = CM_WKUP + 0x48,
+	.cm_clksel_dpll = CM_WKUP + 0x54,
+};
+
+static int get_clk(struct dpll_regs *dpll_regs)
+{
+	unsigned int val;
+	unsigned int m, n;
+	int f = 0;
+
+	val = readl(dpll_regs->cm_clksel_dpll);
+	m = PLL_GET_M(val);
+	n = PLL_GET_N(val);
+	f = (m * V_OSCK) / n;
+
+	return f;
+};
+
+
+
+int clk_get(int clk)
+{
+	return get_clk(&dpll_lcd_regs);
+};
+
+static int conf_disp_pll(int m, int n)
+{
+	struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
+	struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+	struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
+#if defined(DISPL_PLL_SPREAD_SPECTRUM)
+	struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
+#endif
+
+	u32 *const clk_domains[] = {
+		&cmper->lcdclkctrl,
+		0
+	};
+	u32 *const clk_modules_explicit_en[] = {
+		&cmper->lcdclkctrl,
+		&cmper->lcdcclkstctrl,
+		&cmper->spi1clkctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+	/* 0x44e0_0500 write lcdc pixel clock mux Linux hat hier 0 */
+	writel(0x0, &cmdpll->clklcdcpixelclk);
+
+	do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
+
+#if defined(DISPL_PLL_SPREAD_SPECTRUM)
+	writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
+	writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
+	writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12),
+	       &cmwkup->clkmoddplldisp); /* 0x98 */
+#endif
+	return 0;
+}
+
+static int set_gpio(int gpio, int state)
+{
+	gpio_request(gpio, "temp");
+	gpio_direction_output(gpio, state);
+	gpio_set_value(gpio, state);
+	gpio_free(gpio);
+	return 0;
+}
+
+static int enable_lcd(void)
+{
+	unsigned char buf[1];
+
+	set_gpio(BOARD_LCD_RESET, 1);
+
+	/* spi lcd init */
+	kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_3);
+
+	/* backlight on */
+	buf[0] = 0xf;
+	i2c_write(0x24, 0x7, 1, buf, 1);
+	buf[0] = 0x3f;
+	i2c_write(0x24, 0x8, 1, buf, 1);
+	return 0;
+}
+
+int arch_early_init_r(void)
+{
+	enable_lcd();
+	return 0;
+}
+
+static int board_video_init(void)
+{
+	int i;
+	int anzdisp = ARRAY_SIZE(lcd_panels);
+	int display = 1;
+
+	for (i = 0; i < anzdisp; i++) {
+		if (strncmp((const char *)factory_dat.disp_name,
+			    lcd_panels[i].name,
+		    strlen((const char *)factory_dat.disp_name)) == 0) {
+			printf("DISPLAY: %s\n", factory_dat.disp_name);
+			break;
+		}
+	}
+	if (i == anzdisp) {
+		i = 1;
+		printf("%s: %s not found, using default %s\n", __func__,
+		       factory_dat.disp_name, lcd_panels[i].name);
+	}
+	conf_disp_pll(25, 2);
+	da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
+			 lcd_cfgs[display].bpp);
+
+	return 0;
+}
+
+
+#endif /* ifdef CONFIG_VIDEO */
+#include "../common/board.c"
diff --git a/board/siemens/rut/board.h b/board/siemens/rut/board.h
new file mode 100644
index 0000000..0362612
--- /dev/null
+++ b/board/siemens/rut/board.h
@@ -0,0 +1,22 @@
+/*
+ * board.h
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ * u-boot:/board/ti/am335x/board.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/board/siemens/rut/mux.c b/board/siemens/rut/mux.c
new file mode 100644
index 0000000..1eced01
--- /dev/null
+++ b/board/siemens/rut/mux.c
@@ -0,0 +1,347 @@
+/*
+ * pinmux setup for siemens rut board
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux ddr_pin_mux[] = {
+	{OFFSET(ddr_resetn), (MODE(0))},
+	{OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_ck), (MODE(0))},
+	{OFFSET(ddr_nck), (MODE(0))},
+	{OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_ba1), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_ba2), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a0), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a1), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a2), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a3), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a4), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a5), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a6), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a7), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a8), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a9), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a10), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a11), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a12), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a13), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a14), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_a15), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_odt), (MODE(0))},
+	{OFFSET(ddr_d0), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d1), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d2), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d3), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d4), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d5), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d6), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d7), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d8), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d9), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d10), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d11), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d12), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d13), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d14), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_d15), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_dqm0), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_dqm1), (MODE(0) | PULLUP_EN)},
+	{OFFSET(ddr_dqs0), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_dqsn0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(ddr_dqs1), (MODE(0) | RXACTIVE)},
+	{OFFSET(ddr_dqsn1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(ddr_vref), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ddr_vtp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(gpmc_ad8), (MODE(1))},
+	{OFFSET(gpmc_ad9), (MODE(1))},
+	{OFFSET(gpmc_ad10), (MODE(1))},
+	{OFFSET(gpmc_ad11), (MODE(1))},
+	{OFFSET(gpmc_ad12), (MODE(1))},
+	{OFFSET(gpmc_ad13), (MODE(1))},
+	{OFFSET(gpmc_ad14), (MODE(1))},
+	{OFFSET(gpmc_ad15), (MODE(1))},
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},
+	{OFFSET(lcd_vsync), (MODE(0))},
+	{OFFSET(lcd_hsync), (MODE(0))},
+	{OFFSET(lcd_pclk), (MODE(0))},
+	{OFFSET(lcd_ac_bias_en), (MODE(0))},
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux mii_pin_mux[] = {
+	{OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
+	{OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
+	{OFFSET(mii1_txen), (MODE(1))},
+	{OFFSET(mii1_txd1), (MODE(1))},
+	{OFFSET(mii1_txd0), (MODE(1))},
+	{OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
+	{OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
+	{OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
+	{OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	{OFFSET(mii1_col), (MODE(7) | RXACTIVE)},
+	{OFFSET(uart1_ctsn), (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(uart1_rtsn), (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(uart1_txd), (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_txclk), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_rxclk), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_rxd3), (MODE(7) | RXACTIVE)},
+	{OFFSET(mii1_rxd2), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a0), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a1), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a4), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a5), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a6), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a7), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a8), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a10), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_a11), (MODE(7) | RXACTIVE)},
+	{OFFSET(gpmc_wpn), (MODE(7) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(gpmc_be1n), (MODE(7) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(gpmc_csn1), (MODE(7) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(gpmc_csn2), (MODE(7) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(gpmc_csn3), (MODE(7) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mcasp0_aclkr), (MODE(7) | RXACTIVE)},
+	{OFFSET(mcasp0_fsr), (MODE(7))},
+	{OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)},
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE)},
+	{OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(xdma_event_intr1), (MODE(7) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+	{OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux usb0_pin_mux[] = {
+	{OFFSET(usb0_dm), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_dp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_ce), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_id), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_drvvbus), (MODE(0))},
+	{-1},
+};
+
+static struct module_pin_mux usb1_pin_mux[] = {
+	{OFFSET(usb1_dm), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb1_dp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb1_ce), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb1_id), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb1_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb1_drvvbus), (MODE(0))},
+	{-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(spi0_cs1), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux spi1_pin_mux[] = {
+	{OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux jtag_pin_mux[] = {
+	{OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(tdo), (MODE(0) | PULLUP_EN)},
+	{OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(ntrst), (MODE(0) | RXACTIVE)},
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)},
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUP_EN)},
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUP_EN)},
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)},
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux ainx_pin_mux[] = {
+	{OFFSET(ain7), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain6), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain5), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain4), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain3), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain2), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain1), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ain0), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux rtc_pin_mux[] = {
+	{OFFSET(osc1_in), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(osc1_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux gpmc_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(gpmc_clk), (MODE(0) | RXACTIVE)},
+	{-1},
+};
+
+static struct module_pin_mux pmic_pin_mux[] = {
+	{OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux osc_pin_mux[] = {
+	{OFFSET(osc0_in), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(osc0_out), (MODE(0) | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux pwm_pin_mux[] = {
+	{OFFSET(ecap0_in_pwm0_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(gpmc_a2), (MODE(6))},
+	{OFFSET(gpmc_a3), (MODE(6))},
+	{-1},
+};
+
+static struct module_pin_mux emu_pin_mux[] = {
+	{OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux vref_pin_mux[] = {
+	{OFFSET(vrefp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(vrefn), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux misc_pin_mux[] = {
+	{OFFSET(porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)},
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(ddr_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(mii_pin_mux);
+	configure_module_pin_mux(gpio_pin_mux);
+	configure_module_pin_mux(i2c1_pin_mux);
+	configure_module_pin_mux(usb0_pin_mux);
+	configure_module_pin_mux(usb1_pin_mux);
+	configure_module_pin_mux(spi0_pin_mux);
+	configure_module_pin_mux(spi1_pin_mux);
+	configure_module_pin_mux(jtag_pin_mux);
+	configure_module_pin_mux(nand_pin_mux);
+	configure_module_pin_mux(ainx_pin_mux);
+	configure_module_pin_mux(rtc_pin_mux);
+	configure_module_pin_mux(gpmc_pin_mux);
+	configure_module_pin_mux(pmic_pin_mux);
+	configure_module_pin_mux(osc_pin_mux);
+	configure_module_pin_mux(pwm_pin_mux);
+	configure_module_pin_mux(emu_pin_mux);
+	configure_module_pin_mux(vref_pin_mux);
+	configure_module_pin_mux(misc_pin_mux);
+}