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authorPadmavathi Venna <padma.v@samsung.com>2013-03-28 04:32:22 +0000
committerMinkyu Kang <mk7.kang@samsung.com>2013-04-01 14:02:08 +0900
commitf9e4d046e016b81aa5ccf68436b77b12189d418e (patch)
tree00936c8834e5316dd78ad3cd49b0d99254a2b2f6 /board/samsung
parent12a46a384dac2eb0f879394ab39e89dec66df130 (diff)
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Exynos: clock: Correct pwm source clk selection
MPLL is selected as the source clk of pwm by default Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'board/samsung')
-rw-r--r--board/samsung/smdk5250/setup.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h
index a159601..34d8bc31 100644
--- a/board/samsung/smdk5250/setup.h
+++ b/board/samsung/smdk5250/setup.h
@@ -343,7 +343,7 @@
#define TOP2_VAL 0x0110000
/* CLK_SRC_PERIC0 */
-#define PWM_SEL 0
+#define PWM_SEL 6
#define UART3_SEL 6
#define UART2_SEL 6
#define UART1_SEL 6