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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-12-20 19:29:48 +0100
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2009-01-16 10:22:26 +0900
commite4430779623af500de1cee7892c379f07ef59813 (patch)
tree74942b62e37730488c59603d19f045de10c92c1e /board/renesas/rsk7203
parent85cb052ee41675ca361e6a4c69455dc715c8f2d9 (diff)
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sh: lowlevel_init coding style cleanup
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas/rsk7203')
-rw-r--r--board/renesas/rsk7203/lowlevel_init.S214
1 files changed, 107 insertions, 107 deletions
diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S
index e4d6f9e..f6a6231 100644
--- a/board/renesas/rsk7203/lowlevel_init.S
+++ b/board/renesas/rsk7203/lowlevel_init.S
@@ -29,153 +29,153 @@
lowlevel_init:
/* Cache setting */
- mov.l CCR1_A ,r1
- mov.l CCR1_D ,r0
- mov.l r0,@r1
+ mov.l CCR1_A, r1
+ mov.l CCR1_D, r0
+ mov.l r0, @r1
/* ConfigurePortPins */
- mov.l PECRL3_A, r1
- mov.l PECRL3_D, r0
- mov.w r0,@r1
+ mov.l PECRL3_A, r1
+ mov.l PECRL3_D, r0
+ mov.w r0, @r1
- mov.l PCCRL4_A, r1
- mov.l PCCRL4_D0, r0
- mov.w r0,@r1
+ mov.l PCCRL4_A, r1
+ mov.l PCCRL4_D0, r0
+ mov.w r0, @r1
- mov.l PECRL4_A, r1
- mov.l PECRL4_D0, r0
- mov.w r0,@r1
+ mov.l PECRL4_A, r1
+ mov.l PECRL4_D0, r0
+ mov.w r0, @r1
- mov.l PEIORL_A, r1
- mov.l PEIORL_D0, r0
- mov.w r0,@r1
+ mov.l PEIORL_A, r1
+ mov.l PEIORL_D0, r0
+ mov.w r0, @r1
- mov.l PCIORL_A, r1
- mov.l PCIORL_D, r0
- mov.w r0,@r1
+ mov.l PCIORL_A, r1
+ mov.l PCIORL_D, r0
+ mov.w r0, @r1
- mov.l PFCRH2_A, r1
- mov.l PFCRH2_D, r0
- mov.w r0,@r1
+ mov.l PFCRH2_A, r1
+ mov.l PFCRH2_D, r0
+ mov.w r0, @r1
- mov.l PFCRH3_A, r1
- mov.l PFCRH3_D, r0
- mov.w r0,@r1
+ mov.l PFCRH3_A, r1
+ mov.l PFCRH3_D, r0
+ mov.w r0, @r1
- mov.l PFCRH1_A, r1
- mov.l PFCRH1_D, r0
- mov.w r0,@r1
+ mov.l PFCRH1_A, r1
+ mov.l PFCRH1_D, r0
+ mov.w r0, @r1
- mov.l PFIORH_A, r1
- mov.l PFIORH_D, r0
- mov.w r0,@r1
+ mov.l PFIORH_A, r1
+ mov.l PFIORH_D, r0
+ mov.w r0, @r1
- mov.l PECRL1_A, r1
- mov.l PECRL1_D0, r0
- mov.w r0,@r1
+ mov.l PECRL1_A, r1
+ mov.l PECRL1_D0, r0
+ mov.w r0, @r1
- mov.l PEIORL_A, r1
- mov.l PEIORL_D1, r0
- mov.w r0,@r1
+ mov.l PEIORL_A, r1
+ mov.l PEIORL_D1, r0
+ mov.w r0, @r1
/* Configure Operating Frequency */
- mov.l WTCSR_A ,r1
- mov.l WTCSR_D0 ,r0
- mov.w r0,@r1
+ mov.l WTCSR_A, r1
+ mov.l WTCSR_D0, r0
+ mov.w r0, @r1
- mov.l WTCSR_A ,r1
- mov.l WTCSR_D1 ,r0
- mov.w r0,@r1
+ mov.l WTCSR_A, r1
+ mov.l WTCSR_D1, r0
+ mov.w r0, @r1
- mov.l WTCNT_A ,r1
- mov.l WTCNT_D ,r0
- mov.w r0,@r1
+ mov.l WTCNT_A, r1
+ mov.l WTCNT_D, r0
+ mov.w r0, @r1
/* Set clock mode*/
- mov.l FRQCR_A,r1
- mov.l FRQCR_D,r0
- mov.w r0,@r1
+ mov.l FRQCR_A, r1
+ mov.l FRQCR_D, r0
+ mov.w r0, @r1
/* Configure Bus And Memory */
init_bsc_cs0:
- mov.l PCCRL4_A,r1
- mov.l PCCRL4_D1,r0
- mov.w r0,@r1
+ mov.l PCCRL4_A, r1
+ mov.l PCCRL4_D1, r0
+ mov.w r0, @r1
- mov.l PECRL1_A,r1
- mov.l PECRL1_D1,r0
- mov.w r0,@r1
+ mov.l PECRL1_A, r1
+ mov.l PECRL1_D1, r0
+ mov.w r0, @r1
- mov.l CMNCR_A,r1
- mov.l CMNCR_D,r0
- mov.l r0,@r1
+ mov.l CMNCR_A, r1
+ mov.l CMNCR_D, r0
+ mov.l r0, @r1
- mov.l SC0BCR_A,r1
- mov.l SC0BCR_D,r0
- mov.l r0,@r1
+ mov.l SC0BCR_A, r1
+ mov.l SC0BCR_D, r0
+ mov.l r0, @r1
- mov.l CS0WCR_A,r1
- mov.l CS0WCR_D,r0
- mov.l r0,@r1
+ mov.l CS0WCR_A, r1
+ mov.l CS0WCR_D, r0
+ mov.l r0, @r1
init_bsc_cs1:
- mov.l PECRL4_A,r1
- mov.l PECRL4_D1,r0
- mov.w r0,@r1
+ mov.l PECRL4_A, r1
+ mov.l PECRL4_D1, r0
+ mov.w r0, @r1
- mov.l CS1WCR_A,r1
- mov.l CS1WCR_D,r0
- mov.l r0,@r1
+ mov.l CS1WCR_A, r1
+ mov.l CS1WCR_D, r0
+ mov.l r0, @r1
init_sdram:
- mov.l PCCRL2_A,r1
- mov.l PCCRL2_D,r0
- mov.w r0,@r1
+ mov.l PCCRL2_A, r1
+ mov.l PCCRL2_D, r0
+ mov.w r0, @r1
- mov.l PCCRL4_A,r1
- mov.l PCCRL4_D2,r0
- mov.w r0,@r1
+ mov.l PCCRL4_A, r1
+ mov.l PCCRL4_D2, r0
+ mov.w r0, @r1
- mov.l PCCRL1_A,r1
- mov.l PCCRL1_D,r0
- mov.w r0,@r1
+ mov.l PCCRL1_A, r1
+ mov.l PCCRL1_D, r0
+ mov.w r0, @r1
- mov.l PCCRL3_A,r1
- mov.l PCCRL3_D,r0
- mov.w r0,@r1
+ mov.l PCCRL3_A, r1
+ mov.l PCCRL3_D, r0
+ mov.w r0, @r1
- mov.l CS3BCR_A,r1
- mov.l CS3BCR_D,r0
- mov.l r0,@r1
+ mov.l CS3BCR_A, r1
+ mov.l CS3BCR_D, r0
+ mov.l r0, @r1
- mov.l CS3WCR_A,r1
- mov.l CS3WCR_D,r0
- mov.l r0,@r1
+ mov.l CS3WCR_A, r1
+ mov.l CS3WCR_D, r0
+ mov.l r0, @r1
- mov.l SDCR_A,r1
- mov.l SDCR_D,r0
- mov.l r0,@r1
+ mov.l SDCR_A, r1
+ mov.l SDCR_D, r0
+ mov.l r0, @r1
- mov.l RTCOR_A,r1
- mov.l RTCOR_D,r0
- mov.l r0,@r1
+ mov.l RTCOR_A, r1
+ mov.l RTCOR_D, r0
+ mov.l r0, @r1
- mov.l RTCSR_A,r1
- mov.l RTCSR_D,r0
- mov.l r0,@r1
+ mov.l RTCSR_A, r1
+ mov.l RTCSR_D, r0
+ mov.l r0, @r1
/* wait 200us */
- mov.l REPEAT_D,r3
- mov #0,r2
+ mov.l REPEAT_D, r3
+ mov #0, r2
repeat0:
- add #1,r2
- cmp/hs r3,r2
- bf repeat0
+ add #1, r2
+ cmp/hs r3, r2
+ bf repeat0
nop
- mov.l SDRAM_MODE, r1
- mov #0,r0
- mov.l r0, @r1
+ mov.l SDRAM_MODE, r1
+ mov #0, r0
+ mov.l r0, @r1
nop
rts
@@ -208,8 +208,8 @@ PECRL1_D0: .long 0x00000033
WTCSR_A: .long 0xFFFE0000
-WTCSR_D0: .long 0x0000A518
-WTCSR_D1: .long 0x0000A51D
+WTCSR_D0: .long 0x0000A518
+WTCSR_D1: .long 0x0000A51D
WTCNT_A: .long 0xFFFE0002
WTCNT_D: .long 0x00005A84
FRQCR_A: .long 0xFFFE0010
@@ -259,7 +259,7 @@ STBCR4_A: .long 0xFFFE040C
STBCR4_D: .long 0x00000008
STBCR5_A: .long 0xFFFE0410
STBCR5_D: .long 0x00000000
-STBCR6_A: .long 0xFFFE0414
+STBCR6_A: .long 0xFFFE0414
STBCR6_D: .long 0x00000002
SDRAM_MODE: .long 0xFFFC5040
REPEAT_D: .long 0x00009C40