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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-12-20 19:29:49 +0100
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2009-01-16 10:22:27 +0900
commitf7e78f3b74aae9caca2997bad865a72338326c0a (patch)
treeb91ea5c01b9232ffbe7573b5eeac3343b3df8594 /board/renesas/r7780mp
parente4430779623af500de1cee7892c379f07ef59813 (diff)
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sh: use write{8,16,32} in all lowlevel_init
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas/r7780mp')
-rw-r--r--board/renesas/r7780mp/lowlevel_init.S122
1 files changed, 32 insertions, 90 deletions
diff --git a/board/renesas/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S
index 0df8c84..bbea621 100644
--- a/board/renesas/r7780mp/lowlevel_init.S
+++ b/board/renesas/r7780mp/lowlevel_init.S
@@ -22,6 +22,7 @@
#include <config.h>
#include <version.h>
#include <asm/processor.h>
+#include <asm/macro.h>
/*
* Board specific low level init code, called _very_ early in the
@@ -38,63 +39,36 @@
lowlevel_init:
- mov.l CCR_A, r1 /* Address of Cache Control Register */
- mov.l CCR_D, r0 /* Instruction Cache Invalidate */
- mov.l r0, @r1
+ write32 CCR_A, CCR_D /* Address of Cache Control Register */
+ /* Instruction Cache Invalidate */
- mov.l FRQCR_A, r1 /* Frequency control register */
- mov.l FRQCR_D, r0
- mov.l r0, @r1
+ write32 FRQCR_A, FRQCR_D /* Frequency control register */
/* pin_multi_setting */
- mov.l BBG_PMMR_A, r1
- mov.l BBG_PMMR_D_PMSR1, r0
- mov.l r0, @r1
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
- mov.l BBG_PMSR1_A, r1
- mov.l BBG_PMSR1_D, r0
- mov.l r0, @r1
+ write32 BBG_PMSR1_A, BBG_PMSR1_D
- mov.l BBG_PMMR_A, r1
- mov.l BBG_PMMR_D_PMSR2, r0
- mov.l r0, @r1
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
- mov.l BBG_PMSR2_A, r1
- mov.l BBG_PMSR2_D, r0
- mov.l r0, @r1
+ write32 BBG_PMSR2_A, BBG_PMSR2_D
- mov.l BBG_PMMR_A, r1
- mov.l BBG_PMMR_D_PMSR3, r0
- mov.l r0, @r1
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
- mov.l BBG_PMSR3_A, r1
- mov.l BBG_PMSR3_D, r0
- mov.l r0, @r1
+ write32 BBG_PMSR3_A, BBG_PMSR3_D
- mov.l BBG_PMMR_A, r1
- mov.l BBG_PMMR_D_PMSR4, r0
- mov.l r0, @r1
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
- mov.l BBG_PMSR4_A, r1
- mov.l BBG_PMSR4_D, r0
- mov.l r0, @r1
+ write32 BBG_PMSR4_A, BBG_PMSR4_D
- mov.l BBG_PMMR_A, r1
- mov.l BBG_PMMR_D_PMSRG, r0
- mov.l r0, @r1
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
- mov.l BBG_PMSRG_A, r1
- mov.l BBG_PMSRG_D, r0
- mov.l r0, @r1
+ write32 BBG_PMSRG_A, BBG_PMSRG_D
/* cpg_setting */
- mov.l FRQCR_A, r1
- mov.l FRQCR_D, r0
- mov.l r0, @r1
+ write32 FRQCR_A, FRQCR_D
- mov.l DLLCSR_A, r1
- mov.l DLLCSR_D, r0
- mov.l r0, @r1
+ write32 DLLCSR_A, DLLCSR_D
nop
nop
@@ -117,69 +91,37 @@ repeat0:
nop
/* bsc_setting */
- mov.l MMSELR_A, r1
- mov.l MMSELR_D, r0
- mov.l r0, @r1
+ write32 MMSELR_A, MMSELR_D
- mov.l BCR_A, r1
- mov.l BCR_D, r0
- mov.l r0, @r1
+ write32 BCR_A, BCR_D
- mov.l CS0BCR_A, r1
- mov.l CS0BCR_D, r0
- mov.l r0, @r1
+ write32 CS0BCR_A, CS0BCR_D
- mov.l CS1BCR_A, r1
- mov.l CS1BCR_D, r0
- mov.l r0, @r1
+ write32 CS1BCR_A, CS1BCR_D
- mov.l CS2BCR_A, r1
- mov.l CS2BCR_D, r0
- mov.l r0, @r1
+ write32 CS2BCR_A, CS2BCR_D
- mov.l CS4BCR_A, r1
- mov.l CS4BCR_D, r0
- mov.l r0, @r1
+ write32 CS4BCR_A, CS4BCR_D
- mov.l CS5BCR_A, r1
- mov.l CS5BCR_D, r0
- mov.l r0, @r1
+ write32 CS5BCR_A, CS5BCR_D
- mov.l CS6BCR_A, r1
- mov.l CS6BCR_D, r0
- mov.l r0, @r1
+ write32 CS6BCR_A, CS6BCR_D
- mov.l CS0WCR_A, r1
- mov.l CS0WCR_D, r0
- mov.l r0, @r1
+ write32 CS0WCR_A, CS0WCR_D
- mov.l CS1WCR_A, r1
- mov.l CS1WCR_D, r0
- mov.l r0, @r1
+ write32 CS1WCR_A, CS1WCR_D
- mov.l CS2WCR_A, r1
- mov.l CS2WCR_D, r0
- mov.l r0, @r1
+ write32 CS2WCR_A, CS2WCR_D
- mov.l CS4WCR_A, r1
- mov.l CS4WCR_D, r0
- mov.l r0, @r1
+ write32 CS4WCR_A, CS4WCR_D
- mov.l CS5WCR_A, r1
- mov.l CS5WCR_D, r0
- mov.l r0, @r1
+ write32 CS5WCR_A, CS5WCR_D
- mov.l CS6WCR_A, r1
- mov.l CS6WCR_D, r0
- mov.l r0, @r1
+ write32 CS6WCR_A, CS6WCR_D
- mov.l CS5PCR_A, r1
- mov.l CS5PCR_D, r0
- mov.l r0, @r1
+ write32 CS5PCR_A, CS5PCR_D
- mov.l CS6PCR_A, r1
- mov.l CS6PCR_D, r0
- mov.l r0, @r1
+ write32 CS6PCR_A, CS6PCR_D
/* ddr_setting */
/* wait 200us */