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authorVlad Lungu <vlad@comsys.ro>2008-01-16 19:27:51 +0200
committerShinya Kuribayashi <skuribay@ruby.dti.ne.jp>2008-01-17 08:28:08 +0900
commit0764c164fed6277d359cf132d55187ea34290114 (patch)
treef6862e709f1ce4f12a0e5dd0cf9746fa5f7d88c7 /board/qemu-mips/lowlevel_init.S
parent4c9e98ace78e7de972adf7da7135a46ec0a4ee7e (diff)
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MIPS:Target support for qemu -M mips
With serial, NE2000, IDE support. Tested in big-endian mode. Memory size hard-coded to 128M for now, so don't play with the -m option. Signed-off-by: Vlad Lungu <vlad@comsys.ro>
Diffstat (limited to 'board/qemu-mips/lowlevel_init.S')
-rw-r--r--board/qemu-mips/lowlevel_init.S41
1 files changed, 41 insertions, 0 deletions
diff --git a/board/qemu-mips/lowlevel_init.S b/board/qemu-mips/lowlevel_init.S
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--- /dev/null
+++ b/board/qemu-mips/lowlevel_init.S
@@ -0,0 +1,41 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+ .text
+ .set noreorder
+ .set mips32
+
+ .globl lowlevel_init
+lowlevel_init:
+
+ /*
+ * Step 2) Establish Status Register
+ * (set BEV, clear ERL, clear EXL, clear IE)
+ */
+ li t1, 0x00400000
+ mtc0 t1, CP0_STATUS
+
+ /*
+ * Step 3) Establish CP0 Config0
+ * (set K0=3)
+ */
+ li t1, 0x00000003
+ mtc0 t1, CP0_CONFIG
+
+ /*
+ * Step 7) Establish Cause
+ * (set IV bit)
+ */
+ li t1, 0x00800000
+ mtc0 t1, CP0_CAUSE
+
+ /* Establish Wired (and Random) */
+ mtc0 zero, CP0_WIRED
+ nop
+
+ j ra
+ nop