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authorChristoph G. Baumann <c.baumann@ppc-ag.de>2013-10-28 12:29:31 +0100
committerStefano Babic <sbabic@denx.de>2013-10-31 17:54:23 +0100
commit465ac5891c0302d33a59700711f3f0f1e81392fa (patch)
treec047693a9974b64722eb83e031a15e1b6209f608 /board/ppcag/bg0900
parenta0f97610757d6370fc58849032b36a94b4167fdc (diff)
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ARM: mxs: Configure 2 Gbit DDR2 RAM for BG0900
The BG0900 module has 2Gbit DRAM module on it, adjust the DataBahn DRAM controller registers so the DRAM module will be correctly recognised. Signed-off-by: Christoph G. Baumann <c.baumann@ppc-ag.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'board/ppcag/bg0900')
-rw-r--r--board/ppcag/bg0900/spl_boot.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/board/ppcag/bg0900/spl_boot.c b/board/ppcag/bg0900/spl_boot.c
index 2616e1f..a04c955 100644
--- a/board/ppcag/bg0900/spl_boot.c
+++ b/board/ppcag/bg0900/spl_boot.c
@@ -118,6 +118,19 @@ const iomux_cfg_t iomux_setup[] = {
void mxs_adjust_memory_params(uint32_t *dram_vals)
{
+ /*
+ * DDR Controller Registers
+ * Manufacturer: Winbond
+ * Device Part Number: W972GG6JB-25I
+ * Clock Freq.: 200MHz
+ * Density: 2Gb
+ * Chip Selects: 1
+ * Number of Banks: 8
+ * Row address: 14
+ * Column address: 10
+ */
+
+ dram_vals[0x74 / 4] = 0x0102010A;
dram_vals[0x98 / 4] = 0x04005003;
dram_vals[0x9c / 4] = 0x090000c8;