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authorSteve Sakoman <steve@sakoman.com>2010-08-12 21:07:02 -0700
committerSandeep Paulraj <s-paulraj@ti.com>2010-09-08 14:50:47 -0400
commitba9a11e4ea27d43bfc3d9f1787117fe4826b3ce7 (patch)
tree1b9551074897e436613eae7ae1f024dfe1273fd8 /board/overo/overo.h
parent06b95bd50d5a3a09c21271fcf54d2cb849cc453c (diff)
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ARMV7: OMAP: Configure Overo's second network chip
Confiures GPMC timings for both chips and also configures pinmux for GPIO_65, which is used as the interrupt signal for the second chip Signed-off-by: Scott Ellis <scott@jumpnowtek.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'board/overo/overo.h')
-rw-r--r--board/overo/overo.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/overo/overo.h b/board/overo/overo.h
index a4e49b9..2744ffe 100644
--- a/board/overo/overo.h
+++ b/board/overo/overo.h
@@ -138,7 +138,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
/* - SMSC911X_NRES*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
/*DSS*/\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\