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| author | Thierry Reding <treding@nvidia.com> | 2015-08-20 11:42:21 +0200 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-09-16 16:10:23 -0700 |
| commit | 95bdf6469d651076fde0e63a78024e1786a7485d (patch) | |
| tree | 844df4d918c4d326251685f9f0f8f7932e8205ff /board/openrisc/openrisc-generic | |
| parent | 97c02d87f4b08556a36903ce4c5aa9744a95b91e (diff) | |
| download | u-boot-imx-95bdf6469d651076fde0e63a78024e1786a7485d.zip u-boot-imx-95bdf6469d651076fde0e63a78024e1786a7485d.tar.gz u-boot-imx-95bdf6469d651076fde0e63a78024e1786a7485d.tar.bz2 | |
e2220-1170: Remove hard-coded counter frequency
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and allow the timer
setup code to query the correct value at runtime.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/openrisc/openrisc-generic')
0 files changed, 0 insertions, 0 deletions