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authorSimon Glass <sjg@chromium.org>2011-11-05 04:46:51 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-12-24 10:23:31 +0100
commita04eba99f5a00aff54bef32cafa986830b094532 (patch)
tree22aac2fe25a1a1775b4828f65bae2d8958e0304f /board/nvidia/seaboard
parent4560c7decc1b13121072621cee9874e042c059b7 (diff)
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tegra2: Plumb in SPI/UART switch code
On Seaboard the UART and SPI interfere with each other. This causes the UART to receive spurious zero bytes after SPI transactions and also means that SPI can corrupt a few output characters when it starts up if they are still in the UART buffer. This updates the board to use the SPI/UART switch to avoid the problem. For now this feature is turned off since it needs changes to the NS16550 UART to operate. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/nvidia/seaboard')
-rw-r--r--board/nvidia/seaboard/seaboard.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 7f2827b..0b779f6 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -31,6 +31,8 @@
#endif
#include "../common/board.h"
+/* TODO: Remove this code when the SPI switch is working */
+#ifndef CONFIG_SPI_UART_SWITCH
/*
* Routine: gpio_config_uart_seaboard
* Description: Force GPIO_PI3 low on Seaboard so UART4 works.
@@ -48,6 +50,7 @@ void gpio_config_uart(void)
return;
gpio_config_uart_seaboard();
}
+#endif
#ifdef CONFIG_TEGRA2_MMC
/*